公开(公告)号：US20060184908A1

公开(公告)日：2006-08-17

申请号：US11347771

申请日：2006-02-03

申请人： Fumihiro Minami ,  Toshiya Kotani

发明人： Fumihiro Minami ,  Toshiya Kotani

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G03F1/36

摘要： A method for generating layout data of a semiconductor integrated circuit includes applying optical proximity correction conditions to cells so as to generate cell patterns, selecting cell patterns to correspond cells, based on layout information of cells along a specified signal propagating path; calculating delay times for the signal propagating path for combinations of cell patterns; selecting a combination of cell patterns, based on lengths of the calculated delay times and the allowable delay time; and generating layout data of the signal propagating path using the selected combination.

摘要翻译： 一种用于生成半导体集成电路的布局数据的方法包括：对单元施加光学邻近校正条件，以便根据指定的信号传播路径的单元的布局信息产生单元格图形，选择对应单元格的单元图案; 计算用于信元模式组合的信号传播路径的延迟时间; 基于计算的延迟时间的长度和允许的延迟时间来选择单元格图案的组合; 以及使用所选择的组合生成信号传播路径的布局数据。

公开(公告)号：US07370314B2

公开(公告)日：2008-05-06

申请号：US11347771

申请日：2006-02-03

申请人： Fumihiro Minami ,  Toshiya Kotani

发明人： Fumihiro Minami ,  Toshiya Kotani

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G03F1/36

摘要： A method for generating layout data of a semiconductor integrated circuit includes applying optical proximity correction conditions to cells so as to generate cell patterns, selecting cell patterns to correspond cells, based on layout information of cells along a specified signal propagating path; calculating delay times for the signal propagating path for combinations of cell patterns; selecting a combination of cell patterns, based on lengths of the calculated delay times and the allowable delay time; and generating layout data of the signal propagating path using the selected combination.

摘要翻译： 一种用于生成半导体集成电路的布局数据的方法包括：对单元施加光学邻近校正条件，以便根据指定的信号传播路径的单元的布局信息产生单元格图形，选择对应单元格的单元图案; 计算用于信元模式组合的信号传播路径的延迟时间; 基于计算的延迟时间的长度和允许的延迟时间来选择单元格图案的组合; 以及使用所选择的组合生成信号传播路径的布局数据。

公开(公告)号：US20140340923A1

公开(公告)日：2014-11-20

申请号：US14365889

申请日：2012-03-06

申请人： Fumihiro Minami ,  Javier Escobar ,  Takashi Ohsawa

发明人： Fumihiro Minami ,  Javier Escobar ,  Takashi Ohsawa

IPC分类号： F21S8/10 ,  F21K99/00

CPC分类号： F21S41/20 ,  F21S41/14 ,  F21S41/147 ,  F21S41/16 ,  F21S41/255 ,  F21S41/285 ,  F21S41/321 ,  F21S41/36 ,  F21S41/365 ,  F21S41/43 ,  F21S41/60 ,  F21S41/663 ,  F21S45/47

摘要： In an LED2 having a directionality in an emission direction of emitted light, light emitted from a light emitting surface of the LED 2 is refracted by a semi-cylindrical concave lens 3 to be enlarged in the circumference direction of an optical axis of a headlight 1; thus, even when the LED2 is applied to a headlight that is constituted by optical members that are similar to optical members that are compatible with conventional light sources having no directionality, such as an incandescent lamp, a discharge lamp and the like, it can be used as a light source for headlight that is capable of illuminating the right and left directions ahead of a vehicle with a sufficient brightness.

摘要翻译： 在具有发射光的发射方向的方向性的LED2中，从LED2的发光面发射的光被半圆柱形凹透镜3折射，以在头灯1的光轴的圆周方向上扩大 ; 因此，即使将LED2应用于由与诸如白炽灯，放电灯等的不具有方向性的常规光源兼容的光学部件相似的光学部件构成的前照灯，也可以是 用作能够以足够的亮度照亮车辆前方左右方向的头灯的光源。

公开(公告)号：US06813756B2

公开(公告)日：2004-11-02

申请号：US10279403

申请日：2002-10-24

申请人： Mutsunori Igarashi ,  Masami Murakata ,  Takashi Mitsuhashi ,  Masaaki Yamada ,  Fumihiro Minami ,  Takashi Ishioka

发明人： Mutsunori Igarashi ,  Masami Murakata ,  Takashi Mitsuhashi ,  Masaaki Yamada ,  Fumihiro Minami ,  Takashi Ishioka

IPC分类号： G06F1750

CPC分类号： H01L23/528 ,  G06F1/10 ,  G06F17/5077 ,  H01L2924/0002 ,  H01L2924/00

摘要： With an automatic layout method, a first line having a first line width is generated in a prescribed direction. A second line having a second line width and extending at an oblique angle with respect to the first line is generated, so that the second line terminates at an end portion of the first line with an overlapped area. One or more VIA patterns are read out of a database according to the shape of the overlapped area. The VIA patterns are placed in the overlapped area, so that one of the VIA patterns is located at the intersection of the center lines of the first and second lines. The VIA pattern is a combination of parallelograms, including squares and rectangles.

摘要翻译： 利用自动布局方法，在规定的方向上产生具有第一线宽的第一线。 产生具有第二线宽并相对于第一线以倾斜角延伸的第二线，使得第二线终止于第一线的端部处，具有重叠区域。 根据重叠区域的形状，从数据库读出一个或多个VIA图案。 VIA图案被放置在重叠区域中，使得VIA图案之一位于第一和第二行的中心线的交叉处。 VIA模式是平行四边形的组合，包括正方形和矩形。

公开(公告)号：US5557779A

公开(公告)日：1996-09-17

申请号：US417232

申请日：1995-04-05

申请人： Fumihiro Minami

发明人： Fumihiro Minami

IPC分类号： H01L21/82 ,  G06F1/10 ,  G06F17/50 ,  H01L27/02 ,  G06F15/00

CPC分类号： H01L27/0207 ,  G06F1/10 ,  G06F17/5077 ,  G06F2217/62

摘要： A control-signal distributing method used in a wiring-pattern network such that a control signal is supplied from root driver cells via repeating buffer cells to terminal cells. The method comprises the steps of: grouping the terminal cells into clusters containing at least one of the terminal cells, forming a binary-tree-shaped wiring pattern path where the root driver cells are root nodes and the clusters are leaf nodes, inserting the repeating buffer cells into the wiring pattern path at which delay time required for control signal transmission in the binary-tree-shaped path is minimized, calculating first delay amounts in a signal path defined from a branch node at a low level of the binary-tree-shaped path to the leaf nodes, setting physical positions of the branch nodes such that a difference among the calculated first delay amounts is minimized, separating the overlapped terminal cells from each other on the binary-tree-shaped path by updating previous information about a circuit connection when the repeating buffer cells are inserted and by correcting arrangement information about terminal cell positions adjacent to the buffer cells, determining a final wiring-pattern path within each of the clusters based upon the corrected arrangement information, calculating second delay amounts in the clusters based on the finally determined wiring-pattern path, determining respective branch node positions based on the second delay amounts, and determining a final wiring-pattern path among the branch nodes.

摘要翻译： 一种在布线图案网络中使用的控制信号分配方法，使得从根驱动器单元经由重复缓冲器单元向终端单元提供控制信号。 该方法包括以下步骤：将终端小区分组成包含至少一个终端小区的簇，形成二进制树形布线模式路径，其中根驱动单元是根节点，簇是叶节点，插入重复 在二叉树形路径中的控制信号传输所需的延迟时间最小化的布线图案路径中，计算从二进制树形路径的低电平处的分支节点定义的信号路径中的第一延迟量， 设置叶节点的形状路径，设置分支节点的物理位置，使得计算的第一延迟量之间的差异最小化，通过更新关于电路的先前信息在二叉树形路径上将重叠的终端单元彼此分开 连接，并且通过校正与缓冲单元相邻的终端单元位置的布置信息，确定fina 基于校正的布置信息，在每个簇内的布线图案路径，基于最终确定的布线图案路径计算簇中的第二延迟量，基于第二延迟量确定各个分支节点位置，以及确定最终 分支节点之间的布线图案路径。

公开(公告)号：US5410491A

公开(公告)日：1995-04-25

申请号：US896618

申请日：1992-06-10

申请人： Fumihiro Minami

发明人： Fumihiro Minami

IPC分类号： H01L21/82 ,  G06F1/10 ,  G06F17/50 ,  H01L27/02 ,  G06F15/46

CPC分类号： H01L27/0207 ,  G06F1/10 ,  G06F17/5077 ,  G06F2217/62

摘要： A clock-signal distributing method used in a wiring-pattern network such that a clock signal is supplied from root driver cells via repeating buffer cells to terminal cells. The method comprises the steps of: grouping the terminal cells into clusters containing at least one of the terminal cells, forming a binary-tree-shaped wiring pattern path where the root driver cells are root nodes and the clusters are leaf nodes, inserting the repeating buffer cells into the wiring pattern path at which delay time required for clock signal transmission in the binary-tree-shaped path is minimized, calculating first delay amounts in a signal path defined from a branch node at a low level of the binary-tree-shaped path to the leaf nodes, setting physical positions of the branch nodes such that a difference among the calculated first delay amounts is minimized, separating the overlapped terminal cells from each other on the binary-tree-shaped path by updating previous information about a circuit connection when the repeating buffer cells are inserted and by correcting arrangement information about terminal cell positions adjacent to the buffer cells, determining a final wiring-pattern path within each of the clusters based upon the corrected arrangement information, calculating second delay amounts in the clusters based on the finally determined wiring-pattern path, determining respective branch node positions based on the second delay amounts, and determining a final wiring-pattern path among the branch nodes.

摘要翻译： 在布线图形网络中使用的时钟信号分配方法，使得时钟信号从根驱动器单元通过重复缓冲器单元提供给终端单元。 该方法包括以下步骤：将终端小区分组成包含至少一个终端小区的簇，形成二进制树形布线模式路径，其中根驱动单元是根节点，簇是叶节点，插入重复 将二进制树形路径中的时钟信号传输所需的延迟时间最小化的布线图案路径中的缓冲单元计算到从二叉树形路径的低级别的分支节点定义的信号路径中的第一延迟量， 设置叶节点的形状路径，设置分支节点的物理位置，使得计算的第一延迟量之间的差异最小化，通过更新关于电路的先前信息在二叉树形路径上将重叠的终端单元彼此分开 并且通过校正与缓冲单元相邻的终端单元位置的布置信息，确定最终的结果 基于校正的布置信息，在每个簇内的布线图形路径，基于最终确定的布线图案路径计算簇中的第二延迟量，基于第二延迟量确定相应的分支节点位置，以及确定最终布线 分支节点之间的模式路径。

公开(公告)号：US5124273A

公开(公告)日：1992-06-23

申请号：US691613

申请日：1991-02-27

申请人： Fumihiro Minami

发明人： Fumihiro Minami

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A computer-assisted automatic wiring method is presented for logic LSI substrates wherein channel boundary terminals are defined on the boundary line of the first and second channels forming a T-shaped crossing region between the function blocks arranged on a substrate after global wiring process. These channel boundary terminals are roughly divided into the first and second terminal groups there may remain channel boundary terminals which do not belong to any one of the groups. The first terminal group includes terminals intersecting wirings which tend to run along the first direction in the second channel, which corresponds to a top bar of the letter "T". The second terminal group includes terminals intersecting wirings which have tend to run along the second direction opposite to the first direction in said second channel. A pair of channel boundary terminals is sequentially selected from the first and second groups. Typically, the same wiring track is assigned to two wirings associated with the selected each pair of terminals in the second channel.

摘要翻译： 提出了一种用于逻辑LSI基板的计算机辅助自动布线方法，其中通道边界端子限定在第一和第二通道的边界线上，在全局布线处理之后在布置在基板上的功能块之间形成T形交叉区域。 这些信道边界终端大致分为第一和第二终端组，可以保留不属于任一组的信道边界终端。 第一端子组包括在第二通道中沿着第一方向行进的布线相交的端子，其对应于字母“T”的顶部栏。 第二端子组包括沿着与所述第二通道中的第一方向相反的第二方向延伸的布线相交的端子。 从第一组和第二组顺序选择一对通道边界终端。 通常，将相同的接线轨迹分配给与第二通道中所选择的每对端子相关联的两个布线。

公开(公告)号：US07368875B2

公开(公告)日：2008-05-06

申请号：US10895336

申请日：2004-07-21

申请人： Fumihiro Minami ,  Takashi Ohsawa ,  Kinsho Ando

发明人： Fumihiro Minami ,  Takashi Ohsawa ,  Kinsho Ando

IPC分类号： H01J7/44

CPC分类号： H05B41/042

摘要： A through hole that is slightly larger than a size of a rear end of a transformer container is formed in a rear cover constituting a part of an external wall of a starting circuit unit. The transformer container houses therein a transformer and constitutes a transformer portion. The transformer portion is assembled such that a rear end of the transformer container projects from the through hole. This allows the transformer container to constitute a part of the external wall of the starting circuit unit.

摘要翻译： 在构成起动电路单元的外壁的一部分的后盖中形成稍大于变压器容器的后端的尺寸的通孔。 变压器容器内装有变压器并构成变压器部分。 变压器部分被组装成使得变压器容器的后端从通孔突出。 这允许变压器容器构成起动电路单元的外壁的一部分。

公开(公告)号：US20070235766A1

公开(公告)日：2007-10-11

申请号：US11763432

申请日：2007-06-14

申请人： Naohito Kojima ,  Fumihiro Minami ,  Kimiyoshi Usami

发明人： Naohito Kojima ,  Fumihiro Minami ,  Kimiyoshi Usami

IPC分类号： H01L27/10 ,  G06F17/50 ,  H01L21/82

CPC分类号： H01L27/11807 ,  G06F17/5068 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit includes a function block arranged on a substrate, a first buffering cell arranged adjacent to a first side of the function block, a second buffering cell arranged adjacent to a second side adjacent to the first side of the function block, and signal wiring passing over the function block obliquely relative to the first side and the second side, connecting the first buffering cell and the second buffering cell.

摘要翻译： 半导体集成电路包括布置在基板上的功能块，与功能块的第一侧相邻布置的第一缓冲单元，与邻近功能块第一侧相邻的第二侧布置的第二缓冲单元，以及信号 连接第一缓冲单元和第二缓冲单元的布线相对于第一侧和第二侧倾斜地越过功能块。

公开(公告)号：US07075336B2

公开(公告)日：2006-07-11

申请号：US10184425

申请日：2002-06-28

申请人： Naohito Kojima ,  Fumihiro Minami ,  Masami Murakata ,  Takashi Ishioka

发明人： Naohito Kojima ,  Fumihiro Minami ,  Masami Murakata ,  Takashi Ishioka

IPC分类号： H03K19/00 ,  H03K19/096 ,  G06F9/45 ,  G06F17/50 ,  G06F1/12

CPC分类号： G06F17/5045 ,  G06F1/10

摘要： A method for distributing clocks to flip-flop circuits which constitute a logic circuit includes obtaining a timing slack of a first minimum delay time with respect to a minimum delay constraint time and a timing slack of a first maximum delay time with respect to a maximum delay constraint time for a clock in an input path to a flip-flop circuit, obtaining a timing slack of a second minimum delay time with respect to a minimum delay constraint time and a timing slack of a second maximum delay time with respect to a maximum delay constraint time for a clock in an output path from all the flip-flop circuits which receive the clocks from a clock terminal directly and obtaining a delay value which maximizes a minimum value of each of the first and second minimum delay time and maximum delay time of timing slacks.