Abstract:
A solid state drive (SSD) employing a redundant array of independent disks (RAID) scheme includes a flash memory chip, erasable blocks in the flash memory chip, and a flash controller. The erasable blocks are configured to store flash memory pages. The flash controller is operably coupled to the flash memory chip. The flash controller is also configured to organize certain of the flash memory pages into a RAID line group and to write RAID line group membership information to each of the flash memory pages in the RAID line group.
Abstract:
A solid state drive (SSD) employing a redundant array of independent disks (RAID) scheme includes a flash memory chip, erasable blocks in the flash memory chip, and a flash controller. The erasable blocks are configured to store flash memory pages. The flash controller is operably coupled to the flash memory chip. The flash controller is also configured to organize certain of the flash memory pages into a RAID line group and to write RAID line group membership information to each of the flash memory pages in the RAID line group.
Abstract:
A solid state drive (SSD) apparatus includes a plurality of solid state drives. The SSD apparatus also includes a channel-interleaved interface operably coupled to the plurality of solid state drives, the channel-interleaved interface configured to generate interleaved commands including a first command sent on a first channel-interleaved with a second command sent on a second channel in bursts. Additionally, the SSD includes a Peripheral Component Interconnect Express (PCIe) bridge operably coupled to the channel-interleaved interface.
Abstract:
An embodiment solid state drive (SSD) apparatus includes a plurality of computer processing unit (CPU) blades, a channel-interleaved interface operably coupled to the CPU blades, and an input/output (I/O) blade operably coupled to the channel-interleaved interface. In an embodiment, the CPU blades include a processor running a plurality of virtual machines that are locally switched using an Ethernet controller on a chip.