公开(公告)号：US20120260071A1

公开(公告)日：2012-10-11

申请号：US13333631

申请日：2011-12-21

申请人： G. Glenn Henry ,  Gerard M. Col ,  Rodney E. Hooker ,  Terry Parks

发明人： G. Glenn Henry ,  Gerard M. Col ,  Rodney E. Hooker ,  Terry Parks

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F9/345 ,  G06F9/315

CPC分类号： G06F9/30189 ,  G06F9/30072 ,  G06F9/30123 ,  G06F9/30174

摘要： An architectural instruction instructs a microprocessor to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the architectural instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result, determines whether the architectural condition flags satisfy the condition, and updates a non-architectural indicator to indicate whether the architectural condition flags satisfy the condition. To execute the first microinstruction, if the non-architectural indicator updated by the first microinstruction indicates the architectural condition flags satisfy the condition, it updates the destination register with the result; otherwise, it updates the destination register with the current value of the destination register.

摘要翻译： 架构指令指示微处理器对第一和第二源操作数执行操作以产生结果，并且只有在体系结构条件标志满足建筑指令中指定的条件时才将结果写入目的寄存器。 硬件指令翻译器将架构指令转换为第一和第二微指令。 为了执行第一微指令，执行流水线对源操作数执行操作以生成结果，确定架构条件标志是否满足条件，并更新非架构指示符以指示架构条件标志是否满足条件。 为了执行第一微指令，如果由第一微指令更新的非架构指示符指示架构条件标志满足条件，则用结果更新目的寄存器; 否则，它将使用目标寄存器的当前值更新目标寄存器。

公开(公告)号：US20110060943A1

公开(公告)日：2011-03-10

申请号：US12793821

申请日：2010-06-04

申请人： G. Glenn Henry ,  Gerard M. Col ,  Timothy A. Elliott ,  Rodney E. Hooker ,  Terry Parks

发明人： G. Glenn Henry ,  Gerard M. Col ,  Timothy A. Elliott ,  Rodney E. Hooker ,  Terry Parks

IPC分类号： G06F11/14

CPC分类号： G06F9/3865 ,  G06F9/3001 ,  G06F9/30025

摘要： A microprocessor includes a plurality of execution units configured to receive instructions and operands thereof and to execute the instructions. An instruction scheduler issues the instructions to the execution units and selects sources of the instruction operands. At least one of the execution units detects one of the operands of one of the instructions is a denormal operand, generates an indication that the instruction needs to be replayed in response to detecting the denormal operand, and provides the denormal operand to the instruction scheduler in response to detecting the denormal operand, rather than normalizing the denormal operand. The instruction scheduler normalizes the denormal operand, in response to the indication, and causes the normalized operand, rather than the denormal operand, to be provided to the execution unit when the instruction is replayed.

摘要翻译： 微处理器包括被配置为接收其指令和操作数并执行指令的多个执行单元。 指令调度器向执行单元发出指令并选择指令操作数的源。 执行单元中的至少一个检测其中一个指令的操作数之一是反正态操作数，响应于检测到该反正态操作数而产生指示需要重播的指示，并将该反正态操作数提供给指令调度器 对正反操作数进行检测的响应，而不是对正常操作数进行归一化。 指令调度器响应于该指示来对归一化操作数进行归一化，并且当指令被重放时，使归一化操作数而不是反正态操作数提供给执行单元。

公开(公告)号：US07055022B1

公开(公告)日：2006-05-30

申请号：US10279216

申请日：2002-10-22

申请人： Gerard M. Col ,  G. Glenn Henry ,  Terry Parks

发明人： Gerard M. Col ,  G. Glenn Henry ,  Terry Parks

IPC分类号： G06F9/22

CPC分类号： G06F9/322 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/324

摘要： A microprocessor apparatus is provided for performing an indirect near jump operation that includes paired operation translation logic, load logic, and execution logic. The paired operation translation logic receives an indirect near jump macro instruction, and generates a load-jump micro instruction, where the load-jump micro instruction directs load logic to retrieve an offset and directs the execution logic to generate a target address. The load logic is coupled to the paired operation translation logic and receives the load-jump micro instruction. The load logic retrieves the offset from memory, where the offset indicates a jump destination that is relative to an instruction address corresponding to the indirect near jump macro instruction. The execution logic is coupled to the load logic. The execution logic receives the offset, and employs the instruction address and the offset to generate the target address specifying the jump destination for the near jump operation.

摘要翻译： 提供了一种微处理器装置，用于执行包括成对的操作转换逻辑，负载逻辑和执行逻辑的间接近跳转操作。 配对的操作转换逻辑接收间接近跳宏指令，并产生负载跳转微指令，其中负载跳转微指令指示负载逻辑以检索偏移并引导执行逻辑以产生目标地址。 负载逻辑耦合到成对的操作转换逻辑并接收负载跳转微指令。 负载逻辑从存储器检索偏移量，其中偏移量表示相对于间接近跳宏指令对应的指令地址的跳转目的地。 执行逻辑耦合到负载逻辑。 执行逻辑接收偏移量，并采用指令地址和偏移量来生成指定近跳操作的跳转目的地的目标地址。

公开(公告)号：US20140122847A1

公开(公告)日：2014-05-01

申请号：US14007116

申请日：2012-04-06

申请人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

发明人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

IPC分类号： G06F9/26

CPC分类号： G06F9/441 ,  G06F9/265 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30105 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3802 ,  G06F9/4401 ,  G06F9/4403 ,  G06F15/82

摘要： An instruction translator receives a conditional load/store instruction that specifies a condition, destination/data register, base register, offset source, and memory addressing mode. The instruction instructs the microprocessor to load data from a memory location into the destination register (conditional load) or store data to the memory location from the data register (conditional store) only if the condition flags satisfy the condition. The offset source specifies whether the offset is an immediate value or a value in an offset register. The addressing mode specifies whether the base register is updated when the condition flags satisfy the condition. The instruction translator translates the conditional load instruction into a number of microinstructions, which varies as a function of the offset source, addressing mode, and whether the conditional instruction is a conditional load or store instruction. An out-of-order execution pipeline executes the microinstructions to generate results specified by the instruction.

摘要翻译： 指令转换器接收指定条件，目标/数据寄存器，基址寄存器，偏移源和存储器寻址模式的条件加载/存储指令。 只有当条件标志满足条件时，指令才指示微处理器将数据从存储单元加载到目标寄存器（条件加载）中，或者将数据从数据寄存器（条件存储）​​存储到存储单元。 偏移源指定偏移量是立即值还是偏移量寄存器中的值。 寻址模式指定条件标志满足条件时是否更新基址寄存器。 指令翻译器将条件加载指令转换为多个微指令，其作为偏移源，寻址模式以及条件指令是条件加载还是存储指令的函数而变化。 无序执行流水线执行微指令以生成指令指定的结果。

公开(公告)号：US20120260074A1

公开(公告)日：2012-10-11

申请号：US13333520

申请日：2011-12-21

申请人： G. Glenn Henry ,  Gerard M. Col ,  Rodney E. Hooker ,  Terry Parks

发明人： G. Glenn Henry ,  Gerard M. Col ,  Rodney E. Hooker ,  Terry Parks

IPC分类号： G06F9/312 ,  G06F9/315 ,  G06F9/345 ,  G06F9/38

CPC分类号： G06F9/30189 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30141 ,  G06F9/30174

摘要： A microprocessor having performs an architectural instruction that instructs it to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if its architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result. To execute the second microinstruction, it writes the destination register with the result generated by the first microinstruction if the architectural condition flags satisfy the condition, and writes the destination register with the current value of the destination register if the architectural condition flags do not satisfy the condition.

摘要翻译： 一种微处理器，其执行结构指令，指示其在第一和第二源操作数上执行操作以产生结果，并且仅当其结构条件标志满足建筑指令中指定的条件时才将结果写入目的寄存器。 硬件指令转换器将指令转换为第一和第二微指令。 要执行第一个微指令，执行流水线对源操作数执行操作以生成结果。 要执行第二个微指令，如果架构条件标志满足条件，则将目标寄存器写入由第一微指令生成的结果，如果结构条件标志不满足条件标志，则将目标寄存器写入目标寄存器的当前值 条件。

公开(公告)号：US07058794B2

公开(公告)日：2006-06-06

申请号：US10279206

申请日：2002-10-22

申请人： Gerard M. Col ,  G. Glenn Henry ,  Terry Parks

发明人： Gerard M. Col ,  G. Glenn Henry ,  Terry Parks

IPC分类号： G06F9/00

CPC分类号： G06F9/30043 ,  G06F9/30101 ,  G06F9/3017

摘要： A method and apparatus are provided for storing a flags register in a processor. In response to a macro instruction directing the store operation, such as a push flags macro instruction, a mask is generated using privilege level information (i.e., current operating privilege level) to specify those bits of the flags register that can be stored. The mask is then ANDed with contents of the flags register to yield a result and the result is stored on a stack in memory.

摘要翻译： 提供了一种用于将标志寄存器存储在处理器中的方法和装置。 响应于指示存储操作的宏指令（诸如推式标志宏指令），使用特权级别信息（即当前操作特权级别）生成掩码，以指定可存储的标志寄存器的那些位。 然后将掩码与标志寄存器的内容进行AND运算，以产生结果，并将结果存储在内存中的堆栈中。

公开(公告)号：US06591343B1

公开(公告)日：2003-07-08

申请号：US09510211

申请日：2000-02-22

申请人： Gerard M. Col ,  G. Glenn Henry ,  Terry Parks

发明人： Gerard M. Col ,  G. Glenn Henry ,  Terry Parks

IPC分类号： G06F1200

CPC分类号： G06F9/382 ,  G06F9/30152 ,  G06F9/3802 ,  G06F9/3808 ,  G06F12/0846 ,  G06F12/0855 ,  G06F12/1054

摘要： An apparatus and method are provided for determining initial information about a macro instruction prior to decoding of the macro instruction by translation logic within a pipeline microprocessor. The apparatus includes an instruction cache divided into a number of cache ways, each of the cache ways storing a number of cache lines that have been retrieved from memory. As a linear address within a next instruction pointer is provided to retrieve a the macro instruction from the cache, indexed cache lines from each of the cache ways are predecoded by predecode logic. Predecoding is performed in parallel with translation of the linear address to a physical address by translation lookaside buffer logic. The bytes of the indexed cache lines, along with corresponding predecode information fields, are provided to way selection logic. When a cache hit occurs, the way selection logic forwards for translation the cache line bytes and predecode information fields that correspond to the cache way corresponding to the macro instruction.

摘要翻译： 提供了一种装置和方法，用于在流水线微处理器内的转换逻辑解码宏指令之前确定关于宏指令的初始信息。 该装置包括被分成多个高速缓存路径的指令高速缓存，每个高速缓存路径存储已经从存储器检索的多条高速缓存行。 由于提供下一个指令指针中的线性地址以从高速缓存中检索宏指令，所以每个缓存方式的索引高速缓存行都由预解码逻辑进行预解码。 通过平移后备缓冲器逻辑将线性地址转换为物理地址并行执行预编码。 索引高速缓存行的字节连同对应的预先解码信息字段被提供给方式选择逻辑。 当发生高速缓存命中时，选择逻辑将转发用于转换与对应于宏指令的缓存方式对应的高速缓存行字节和预解码信息字段。

公开(公告)号：US09645822B2

公开(公告)日：2017-05-09

申请号：US14007097

申请日：2012-04-06

申请人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

发明人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

IPC分类号： G06F9/30

CPC分类号： G06F9/3017 ,  G06F9/30076 ,  G06F9/30123 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196

摘要： An instruction translator translates a conditional store instruction (specifying data register, base register, and offset register of the register file) into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives a base value and an offset from the register file and generates a first result as a function of the base value and offset. The first result specifies the memory location address. To execute a second microinstruction, an execution unit receives the first result and writes the first result to an allocated entry in the store queue if the condition flags satisfy the condition (the store queue subsequently writes the data to the memory location specified by the address), and otherwise kills the allocated store queue entry so that the store queue does not write the data to the memory location specified by the address.

公开(公告)号：US20140122843A1

公开(公告)日：2014-05-01

申请号：US14007097

申请日：2012-04-06

申请人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

发明人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3017 ,  G06F9/30076 ,  G06F9/30123 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196

摘要： An instruction translator translates a conditional store instruction (specifying data register, base register, and offset register of the register file) into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives a base value and an offset from the register file and generates a first result as a function of the base value and offset. The first result specifies the memory location address. To execute a second microinstruction, an execution unit receives the first result and writes the first result to an allocated entry in the store queue if the condition flags satisfy the condition (the store queue subsequently writes the data to the memory location specified by the address), and otherwise kills the allocated store queue entry so that the store queue does not write the data to the memory location specified by the address.

摘要翻译： 指令翻译器将条件存储指令（指定寄存器文件的指定数据寄存器，基址寄存器和偏移寄存器）转换为至少两个微指令。 无序执行管线执行微指令。 为了执行第一微指令，执行单元从寄存器文件接收基值和偏移量，并且产生作为基值和偏移量的函数的第一结果。 第一个结果指定内存位置地址。 为了执行第二微指令，如果条件标志满足条件（存储队列随后将数据写入由地址指定的存储器位置），则执行单元接收第一结果并将第一结果写入存储队列中的已分配条目， ，否则将杀死所分配的存储队列条目，使得存储队列不将数据写入由地址指定的存储器位置。

公开(公告)号：US08495343B2

公开(公告)日：2013-07-23

申请号：US12793821

申请日：2010-06-04

申请人： G. Glenn Henry ,  Gerard M. Col ,  Timothy A. Elliott ,  Rodney E. Hooker ,  Terry Parks

发明人： G. Glenn Henry ,  Gerard M. Col ,  Timothy A. Elliott ,  Rodney E. Hooker ,  Terry Parks

IPC分类号： G06F9/00

CPC分类号： G06F9/3865 ,  G06F9/3001 ,  G06F9/30025

摘要： A microprocessor includes a plurality of execution units configured to receive instructions and operands thereof and to execute the instructions. An instruction scheduler issues the instructions to the execution units and selects sources of the instruction operands. At least one of the execution units detects one of the operands of one of the instructions is a denormal operand, generates an indication that the instruction needs to be replayed in response to detecting the denormal operand, and provides the denormal operand to the instruction scheduler in response to detecting the denormal operand, rather than normalizing the denormal operand. The instruction scheduler normalizes the denormal operand, in response to the indication, and causes the normalized operand, rather than the denormal operand, to be provided to the execution unit when the instruction is replayed.

摘要翻译： 微处理器包括被配置为接收其指令和操作数并执行指令的多个执行单元。 指令调度器向执行单元发出指令并选择指令操作数的源。 执行单元中的至少一个检测其中一个指令的操作数之一是反正态操作数，响应于检测到该反正态操作数而产生指示需要重播的指示，并将该反正态操作数提供给指令调度器 对正反操作数进行检测的响应，而不是对正常操作数进行归一化。 指令调度器响应于该指示来对归一化操作数进行归一化，并且当指令被重放时，使归一化操作数而不是反正态操作数提供给执行单元。