公开(公告)号：US10218346B1

公开(公告)日：2019-02-26

申请号：US15704458

申请日：2017-09-14

Applicant: GaN Systems Inc.

Inventor： Ahmad Mizan ,  Greg P. Klowak ,  Xiaodong Cui

IPC: H01L29/20 ,  H01L23/522 ,  H01L29/778 ,  H03K17/081 ,  H01L29/205 ,  H01L23/528 ,  H01L29/06 ,  H01L23/532 ,  H01L23/31

Abstract: Large area, high current, lateral GaN power transistors are implemented using an on-chip interconnect topology wherein the transistor is arranged as an array of sections, each section comprising a set of transistor islands; gate and source buses that form each gate drive loop have substantially the same track widths; the source bus runs over or under the gate bus, and the tracks are inductively coupled to provide flux cancellation in the gate drive loop, thereby reducing parasitic inductances. The gate delay in each gate drive loop is reduced, minimizing the gate drive phase difference across the transistor. An overlying current redistribution layer preferably has a track width no greater than that of the underlying source and drain buses, for efficient coupling. This topology provides improved scalability, enabling fabrication of multi-section, large scale, high current lateral GaN transistors with reduced gate drive loop inductance, for improved operational stability.

公开(公告)号：US09660639B2

公开(公告)日：2017-05-23

申请号：US15091867

申请日：2016-04-06

Applicant: GaN Systems Inc.

Inventor： John Roberts ,  Ahmad Mizan

IPC: H03K3/00 ,  H03K17/16 ,  H03K17/687 ,  H01L29/20 ,  H01L29/40 ,  H01L29/417

CPC classification number: H03K17/162 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H03K17/168 ,  H03K17/6877

Abstract: Power switching systems are disclosed comprising driver circuitry for enhancement-mode (E-Mode) GaN power transistors with low threshold voltage. Preferably, a GaN power switch (D3) comprises an E-Mode high electron mobility transistor (HEMT) with a monolithically integrated GaN driver. D3 is partitioned into sections. At least the pull-down and, optionally, the pull-up driver circuitry is similarly partitioned as a plurality of driver elements, each driving a respective section of D3. Each driver element is placed in proximity to a respective section of D3, reducing interconnect track length and loop inductance. In preferred embodiments, the layout of GaN transistor switch and the driver elements, dimensions and routing of the interconnect tracks are selected to further reduce loop inductance and optimize performance. Distributed driver circuitry integrated on-chip with one or more high power E-Mode GaN switches allows closer coupling of the driver circuitry and the GaN switches to reduce effects of parasitic inductances.

公开(公告)号：US09153509B2

公开(公告)日：2015-10-06

申请号：US14568507

申请日：2014-12-12

Applicant: GAN SYSTEMS INC.

Inventor： Gregory P. Klowak ,  Cameron McKnight-MacNeil ,  Howard Tweddle ,  Ahmad Mizan ,  Nigel Springett

IPC: H01L29/768 ,  H01L31/113 ,  H01L21/82 ,  H01L21/336 ,  H01L21/66 ,  H01L29/20 ,  H01L29/201 ,  H01L29/205 ,  H01L29/778 ,  H01L27/095 ,  H01L23/528

CPC classification number: H01L29/7787 ,  H01L22/14 ,  H01L22/22 ,  H01L22/32 ,  H01L23/4824 ,  H01L23/528 ,  H01L27/095 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighboring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.

Abstract translation: 提供了大面积氮化物半导体器件的容错设计，便于测试和隔离缺陷区域。 晶体管包括多个岛的阵列，每个岛包括有源区，源极和漏极以及栅电极。 每个岛的电极在阵列的至少一个方向上与相邻岛的电极电隔离。 提供源极，漏极和栅极接触焊盘，以实现每个岛的电气测试。 在岛的电测试以识别有缺陷的岛之后，形成覆盖的电连接以使源电极并联连接，漏电极并联，并且互连栅电极以形成具有大栅极宽度Wg的公共栅电极。 选择性地向好的岛屿提供互连，同时电隔离有缺陷的岛屿。 这种方法使得制造大面积GaN器件（包括混合器件）在经济上是可行的。