公开(公告)号：US09368420B2

公开(公告)日：2016-06-14

申请号：US14732689

申请日：2015-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephen W. Bedell ,  Wilfried E. Haensch ,  Bahman Hekmatshoartabari ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L27/01 ,  H01L23/14 ,  H01L27/12 ,  H01L27/092 ,  H01L23/538 ,  H01L21/762

CPC classification number: H01L23/14 ,  H01L21/4846 ,  H01L21/7624 ,  H01L23/5381 ,  H01L23/5386 ,  H01L23/5387 ,  H01L27/092 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Fabrication methods are disclosed that facilitate the production of electronic structures that are both flexible and stretchable to conform to non-planar (e.g. curved) surfaces without suffering functional damage due to excessive strain. Electronic structures including CMOS devices are provided that can be stretched or squeezed within acceptable limits without failing or breaking. The methods disclosed herein further facilitate the production of flexible, stretchable electronic structures having multiple levels of intra-chip connectors. Such connectors are formed through deposition and photolithographic patterning (back end of the line processing) and can be released following transfer of the electronic structures to flexible substrates.

公开(公告)号：US09356114B2

公开(公告)日：2016-05-31

申请号：US14042951

申请日：2013-10-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kevin K. Chan ,  Bahman Hekmatshoartabari ,  Tak H. Ning ,  Davood Shahrjerdi

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/283 ,  H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L21/308

CPC classification number: H01L29/66242 ,  H01L21/283 ,  H01L21/3086 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/7371

Abstract: A method of forming the heterojunction bipolar transistor that includes providing a stack of a base layer, an extrinsic base layer, a first metal containing layer, and a dielectric cap layer. The dielectric cap layer and the first metal containing layer may be etched to provide a base contact and a dielectric cap. Exposed portions of the base layer may be etched selectively to the dielectric cap. A remaining portion of the base layer provides the base region. A hydrogenated silicon containing layer may be deposited with a low temperature deposition method. At least a portion of the hydrogenated silicon containing layer is formed on at least sidewalls of the base region. A second metal containing layer may be formed on the hydrogenated silicon containing layer. The second metal containing and the hydrogenated silicon containing layer may be etched to provide an emitter region and a collector region.

Abstract translation: 一种形成异质结双极晶体管的方法，其包括提供基底层，非本征基底层，第一金属含量层和电介质盖层的叠层。 可以蚀刻电介质盖层和第一含金属层以提供基极接触和电介质盖。 基底层的暴露部分可以选择性地蚀刻到电介质盖。 基层的剩余部分提供基区。 可以用低温沉积法沉积氢化含硅层。 氢化含硅层的至少一部分形成在基底区域的至少侧壁上。 可以在含氢硅层上形成第二含金属层。 可以蚀刻包含第二金属和含氢硅的层，以提供发射极区域和集电极区域。

公开(公告)号：US09224755B2

公开(公告)日：2015-12-29

申请号：US14020098

申请日：2013-09-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L21/00 ,  H01L27/12 ,  H01L21/762

CPC classification number: H01L27/3262 ,  H01L21/7624 ,  H01L21/76254 ,  H01L27/1218 ,  H01L27/1262 ,  H01L27/1266 ,  H01L27/3248 ,  H01L51/5218 ,  H01L51/5221 ,  H01L51/5237 ,  H01L2227/323 ,  H01L2227/326 ,  H01L2251/5338

Abstract: High resolution active matrix structures are fabricated using techniques applicable to flexible substrates. A backplane layer including active semiconductor devices is formed using a semiconductor-on-insulator substrate. The substrate is thinned using a layer transfer technique or chemical/mechanical processing. Driver transistors are formed on the semiconductor layer of the substrate along with additional circuits that provide other functions such as computing or sensing. Contacts to passive devices such as organic light emitting diodes may be provided by heavily doped regions formed in the handle layer of the substrate and then isolated. A gate dielectric layer may be formed on the semiconductor layer, which functions as a channel layer, or the insulator layer of the substrate may be employed as a gate dielectric layer.

Abstract translation: 使用适用于柔性基板的技术制造高分辨率有源矩阵结构。 包括有源半导体器件的背板层使用绝缘体上半导体衬底形成。 使用层转移技术或化学/机械加工使衬底变薄。 在衬底的半导体层上形成驱动晶体管以及提供计算或感测等其它功能的附加电路。 与诸如有机发光二极管的无源器件的接触可以由形成在衬底的手柄层中的重掺杂区域提供，然后被隔离。 可以在用作沟道层的半导体层上形成栅极电介质层，或者可以将衬底的绝缘体层用作栅极介电层。