中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

17 records (took 0.016 seconds)

    Integrated finFET-BJT replacement metal gate
    1.
    发明授权
    Integrated finFET-BJT replacement metal gate 有权
    集成finFET-BJT替换金属门

    公开(公告)号：US09263583B2

    公开(公告)日：2016-02-16

    申请号：US14052924

    申请日：2013-10-14

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jin Cai ,  Effendi Leobandung ,  Tak H. Ning

    IPC: H01L29/78 ,  H01L29/73 ,  H01L21/8222 ,  H01L21/8248

    CPC classification number: H01L29/785 ,  H01L21/8222 ,  H01L21/823821 ,  H01L21/8248 ,  H01L21/8249 ,  H01L21/845 ,  H01L27/0623 ,  H01L27/0924 ,  H01L29/6625 ,  H01L29/66545 ,  H01L29/73 ,  H01L29/735

    Abstract: A method of forming a semiconductor structure that includes forming a first recess and a second recess between a first pair of sidewall spacers and a second pair of sidewall spacers respectively, the first and second pair of sidewall spacers surrounding a fin on top of a buried dielectric layer, the fin is formed from a top most semiconductor layer of a semiconductor-on-insulator substrate. A high-k dielectric layer is deposited within the first and second recesses and a dummy titanium nitride layer is deposited on the high-k dielectric layer. The high-k dielectric layer and the dummy titanium nitride layer are removed from the second recess and a silicon cap layer is deposited within the first and second recesses. Next, dopants are implanted into the silicon cap layer in the second recess without implanting dopants into the silicon cap layer in the first recess to form a BJT device.

    Abstract translation: 一种形成半导体结构的方法，包括在第一对侧壁间隔件和第二对侧壁间隔物之间​​分别形成第一凹部和第二凹槽，所述第一和第二对侧壁间隔件围绕埋在电介质顶部的翅片 层，由绝缘体上半导体衬底的最上半导体层形成鳍。 高k电介质层沉积在第一和第二凹槽内，并且在高k电介质层上沉积虚拟氮化钛层。 从第二凹部去除高k电介质层和虚拟氮化钛层，并且在第一和第二凹槽内沉积硅帽层。 接下来，将掺杂剂注入到第二凹槽中的硅帽层中，而不将掺杂剂注入到第一凹槽中的硅帽层中以形成BJT器件。

    Lateral BiCMOS replacement metal gate
    5.
    发明授权
    Lateral BiCMOS replacement metal gate 有权

    公开(公告)号：US10192864B2

    公开(公告)日：2019-01-29

    申请号：US15264885

    申请日：2016-09-14

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jin Cai ,  Effendi Leobandung ,  Tak H. Ning

    IPC: H01L27/06 ,  H01L21/8249 ,  H01L27/092 ,  H01L29/66

    Abstract: A method of forming a semiconductor structure includes depositing a high-k dielectric layer within a first recess located between sidewall spacers of a first CMOS device and within a second recess located between sidewall spacers of a second CMOS device. A dummy titanium nitride layer is deposited on the high-k dielectric layer. Next, the high-k dielectric layer and the dummy titanium nitride layer are removed from the second recess in the second CMOS device. A silicon cap layer is deposited within the first recess and the second recess, the silicon cap layer is located above the high-k dielectric layer and dummy titanium nitride layer in the first CMOS device. Subsequently, dopants are implanted into the silicon cap layer located in the second recess of the second CMOS device.

    Lateral BiCMOS replacement metal gate
    9.
    发明授权
    Lateral BiCMOS replacement metal gate 有权
    横向BiCMOS替换金属门

    公开(公告)号：US09478534B2

    公开(公告)日：2016-10-25

    申请号：US14048131

    申请日：2013-10-08

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jin Cai ,  Effendi Leobandung ,  Tak H. Ning

    IPC: H01L21/8249 ,  H01L27/06

    CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L27/092 ,  H01L29/66545

    Abstract: A method of forming a semiconductor structure includes depositing a high-k dielectric layer within a first recess located between sidewall spacers of a first CMOS device and within a second recess located between sidewall spacers of a second CMOS device. A dummy titanium nitride layer is deposited on the high-k dielectric layer. Next, the high-k dielectric layer and the dummy titanium nitride layer are removed from the second recess in the second CMOS device. A silicon cap layer is deposited within the first recess and the second recess, the silicon cap layer is located above the high-k dielectric layer and dummy titanium nitride layer in the first CMOS device. Subsequently, dopants are implanted into the silicon cap layer located in the second recess of the second CMOS device.

    Abstract translation: 形成半导体结构的方法包括在位于第一CMOS器件的侧壁间隔件之间的第一凹槽内以及位于第二CMOS器件的侧壁间隔物之间​​的第二凹槽内沉积高k电介质层。 在高k电介质层上沉积虚拟氮化钛层。 接下来，从第二CMOS器件的第二凹部去除高k电介质层和虚拟氮化钛层。 在第一凹槽和第二凹槽中沉积硅帽层，硅帽层位于第一CMOS器件中的高k电介质层和虚拟氮化钛层的上方。 随后，将掺杂剂注入到位于第二CMOS器件的第二凹槽中的硅帽层中。

Patent Agency Ranking