公开(公告)号：US09236499B2

公开(公告)日：2016-01-12

申请号：US14496285

申请日：2014-09-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kevin K. Chan ,  John J. Ellis-Monaghan ,  David L. Harame ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/808 ,  H01L29/732 ,  H01L29/66 ,  H01L29/737 ,  H01L29/10 ,  H01L27/06 ,  G06F17/50 ,  H01L29/16 ,  H01L29/161 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L29/8086 ,  G06F17/5045 ,  H01L27/0623 ,  H01L29/0817 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/1058 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/808

Abstract: Junction field-effect transistors and design structures for a junction field-effect transistor. A source and a drain of the junction field-effect transistor are comprised of a semiconductor material grown by selective epitaxy and in direct contact with a top surface of a semiconductor layer. A gate is formed that is aligned with a channel laterally disposed in the semiconductor layer between the source and the drain. The source, the drain, and the semiconductor layer are each comprised of a second semiconductor material having an opposite conductivity type from a first semiconductor material comprising the gate.

Abstract translation: 结场效应晶体管和结型场效应晶体管的设计结构。 结场效应晶体管的源极和漏极由通过选择性外延生长并与半导体层的顶表面直接接触的半导体材料组成。 形成与在源极和漏极之间横向设置在半导体层中的沟道对准的栅极。 源极，漏极和半导体层各自包括与包括栅极的第一半导体材料具有相反导电类型的第二半导体材料。

公开(公告)号：US08618617B2

公开(公告)日：2013-12-31

申请号：US13783526

申请日：2013-03-04

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kevin K. Chan ,  Abhishek Dube ,  Eric C. Harley ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman ,  Linda R. Black

IPC: H01L27/088

CPC classification number: H01L29/7848 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78684

Abstract: A method for forming a field effect transistor device includes forming a gate stack portion on a substrate, forming a spacer portion on the gates stack portion and a portion of the substrate, removing an exposed portion of the substrate, epitaxially growing a first silicon material on the exposed portion of the substrate, removing a portion of the epitaxially grown first silicon material to expose a second portion of the substrate, and epitaxially growing a second silicon material on the exposed second portion of the substrate and the first silicon material.

Abstract translation: 一种用于形成场效应晶体管器件的方法，包括：在衬底上形成栅极叠层部分，在栅堆叠部分和衬底的一部分上形成间隔部分，去除衬底的暴露部分，将第一硅材料外延生长 衬底的暴露部分，去除外延生长的第一硅材料的一部分以暴露衬底的第二部分，以及在衬底的暴露的第二部分和第一硅材料上外延生长第二硅材料。

公开(公告)号：US09356114B2

公开(公告)日：2016-05-31

申请号：US14042951

申请日：2013-10-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kevin K. Chan ,  Bahman Hekmatshoartabari ,  Tak H. Ning ,  Davood Shahrjerdi

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/283 ,  H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L21/308

CPC classification number: H01L29/66242 ,  H01L21/283 ,  H01L21/3086 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/7371

Abstract: A method of forming the heterojunction bipolar transistor that includes providing a stack of a base layer, an extrinsic base layer, a first metal containing layer, and a dielectric cap layer. The dielectric cap layer and the first metal containing layer may be etched to provide a base contact and a dielectric cap. Exposed portions of the base layer may be etched selectively to the dielectric cap. A remaining portion of the base layer provides the base region. A hydrogenated silicon containing layer may be deposited with a low temperature deposition method. At least a portion of the hydrogenated silicon containing layer is formed on at least sidewalls of the base region. A second metal containing layer may be formed on the hydrogenated silicon containing layer. The second metal containing and the hydrogenated silicon containing layer may be etched to provide an emitter region and a collector region.

Abstract translation: 一种形成异质结双极晶体管的方法，其包括提供基底层，非本征基底层，第一金属含量层和电介质盖层的叠层。 可以蚀刻电介质盖层和第一含金属层以提供基极接触和电介质盖。 基底层的暴露部分可以选择性地蚀刻到电介质盖。 基层的剩余部分提供基区。 可以用低温沉积法沉积氢化含硅层。 氢化含硅层的至少一部分形成在基底区域的至少侧壁上。 可以在含氢硅层上形成第二含金属层。 可以蚀刻包含第二金属和含氢硅的层，以提供发射极区域和集电极区域。

公开(公告)号：US09349649B2

公开(公告)日：2016-05-24

申请号：US14315844

申请日：2014-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kevin K. Chan ,  Yue Ke ,  Annie Levesque ,  Dae-Gyu Park ,  Ravikumar Ramachandran ,  Amanda L. Tessier ,  Min Yang

IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L21/223 ,  H01L21/265 ,  H01L27/088 ,  H01L29/08 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/823431 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/223 ,  H01L21/2236 ,  H01L21/26566 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7853

Abstract: A gate structure is formed straddling a first portion of a plurality of semiconductor fins that extend upwards from a topmost surface of an insulator layer. A dielectric spacer is formed on sidewalls of the gate structure and straddling a second portion of the plurality of semiconductor fins. Epitaxial semiconductor material portions that include a non-planar bottommost surface and a non-planar topmost surface are grown from at least the exposed sidewalls of each semiconductor fin not including the gate structure or the gate spacer to merge adjacent semiconductor fins. A gap is present beneath epitaxial semiconductor material portions and the topmost surface of the insulator layer. A second epitaxial semiconductor material is formed on the epitaxial semiconductor material portions and thereafter the second epitaxial semiconductor material is converted into a metal semiconductor alloy.

公开(公告)号：US09023697B2

公开(公告)日：2015-05-05

申请号：US13962322

申请日：2013-08-08

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kevin K. Chan ,  Dae-Gyu Park ,  Xinhui Wang ,  Yun-Yu Wang ,  Min Yang ,  Qi Zhang

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0924 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes growing an epitaxial doped layer over an exposed portion of a plurality of fins. The epitaxial doped layer combines the exposed portion of the fins to form a merged source and drain region. An implantation process occurs in the fins through the epitaxial doped layer to change the crystal lattice of the fins to form amorphized fins. A nitride layer is deposited over the semiconductor structure. The nitride layer covers the merged source and drain regions. A thermal treatment is performed in the semiconductor structure to re-crystallize the amorphized fins to form re-crystallized fins. The re-crystallized fins, the epitaxial doped layer and the nitride layer form a strained source and drain region which induces stress to a channel region.

Abstract translation: 形成半导体结构的方法包括在多个鳍片的暴露部分上生长外延掺杂层。 外延掺杂层将散热片的暴露部分组合以形成合并的源极和漏极区域。 通过外延掺杂层在鳍片中发生注入工艺，以改变鳍片的晶格以形成非晶化鳍片。 氮化物层沉积在半导体结构上。 氮化物层覆盖合并的源区和漏区。 在半导体结构中进行热处理以使非晶化翅片再结晶以形成再结晶的翅片。 再结晶的翅片，外延掺杂层和氮化物层形成应变源极和漏极区域，其对沟道区域引起应力。

公开(公告)号：US09275907B2

公开(公告)日：2016-03-01

申请号：US14522649

申请日：2014-10-24

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, INC.

Inventor： Kevin K. Chan ,  Dae-Gyu Park ,  Xinhui Wang ,  Yun-Yu Wang ,  Min Yang ,  Qi Zhang

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L21/265

CPC classification number: H01L21/823821 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0924 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes growing an epitaxial doped layer over an exposed portion of a plurality of fins. The epitaxial doped layer combines the exposed portion of the fins to form a merged source and drain region. An implantation process occurs in the fins through the epitaxial doped layer to change the crystal lattice of the fins to form amorphized fins. A nitride layer is deposited over the semiconductor structure. The nitride layer covers the merged source and drain regions. A thermal treatment is performed in the semiconductor structure to re-crystallize the amorphized fins to form re-crystallized fins. The re-crystallized fins, the epitaxial doped layer and the nitride layer form a strained source and drain region which induces stress to a channel region.

公开(公告)号：US20130175547A1

公开(公告)日：2013-07-11

申请号：US13783526

申请日：2013-03-04

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kevin K. Chan ,  Abhishek Dube ,  Eric C. Harley ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman ,  Linda R. Black

IPC: H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78684

Abstract: A method for forming a field effect transistor device includes forming a gate stack portion on a substrate, forming a spacer portion on the gates stack portion and a portion of the substrate, removing an exposed portion of the substrate, epitaxially growing a first silicon material on the exposed portion of the substrate, removing a portion of the epitaxially grown first silicon material to expose a second portion of the substrate, and epitaxially growing a second silicon material on the exposed second portion of the substrate and the first silicon material.

Abstract translation: 一种用于形成场效应晶体管器件的方法，包括：在衬底上形成栅极叠层部分，在栅堆叠部分和衬底的一部分上形成间隔部分，去除衬底的暴露部分，将第一硅材料外延生长 衬底的暴露部分，去除外延生长的第一硅材料的一部分以暴露衬底的第二部分，以及在衬底的暴露的第二部分和第一硅材料上外延生长第二硅材料。

公开(公告)号：US09437717B2

公开(公告)日：2016-09-06

申请号：US13971982

申请日：2013-08-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kevin K. Chan ,  Peng Cheng ,  Qizhi Liu ,  Ljubo Radic

IPC: H01L29/73 ,  H01L29/66 ,  H01L29/737 ,  H01L29/10 ,  G06F17/50

CPC classification number: H01L29/73 ,  G06F17/5045 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7371

Abstract: Methods of fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. A first portion of the intrinsic base layer is masked while a second portion of an intrinsic base layer is etched. As a consequence of the masking, the second portion of the intrinsic base layer is thinner than the first portion of the intrinsic base layer. An emitter and an extrinsic base layer are formed in respective contacting relationships with the first and second portions of the intrinsic base layer.

公开(公告)号：US09349650B2

公开(公告)日：2016-05-24

申请号：US14524246

申请日：2014-10-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kevin K. Chan ,  Yue Ke ,  Annie Levesque ,  Dae-Gyu Park ,  Ravikumar Ramachandran ,  Amanda L. Tessier ,  Min Yang

IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L21/223 ,  H01L21/265 ,  H01L27/088 ,  H01L29/08

CPC classification number: H01L21/823431 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/223 ,  H01L21/2236 ,  H01L21/26566 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7853

Abstract: A gate structure is formed straddling a first portion of a plurality of semiconductor fins that extend upwards from a topmost surface of an insulator layer. A dielectric spacer is formed on sidewalls of the gate structure and straddling a second portion of the plurality of semiconductor fins. Epitaxial semiconductor material portions that include a non-planar bottommost surface and a non-planar topmost surface are grown from at least the exposed sidewalls of each semiconductor fin not including the gate structure or the gate spacer to merge adjacent semiconductor fins. A gap is present beneath epitaxial semiconductor material portions and the topmost surface of the insulator layer. A second epitaxial semiconductor material is formed on the epitaxial semiconductor material portions and thereafter the second epitaxial semiconductor material is converted into a metal semiconductor alloy.

Abstract translation: 栅极结构跨越从绝缘体层的最上表面向上延伸的多个半导体鳍片的第一部分形成。 介电隔离件形成在栅极结构的侧壁上并且跨越多个半导体鳍片的第二部分。 至少从不包括栅极结构或栅极间隔物的半导体鳍片的暴露的侧壁至少生长包括非平面最底表面和非平面最上表面的外延半导体材料部分，以使相邻的半导体鳍片合流。 在外延半导体材料部分和绝缘体层的最上表面之下存在间隙。 在外延半导体材料部分上形成第二外延半导体材料，然后将第二外延半导体材料转换成金属半导体合金。