公开(公告)号：US10439064B1

公开(公告)日：2019-10-08

申请号：US15990956

申请日：2018-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Randy W. Mann ,  Bipul C. Paul

IPC: H01L23/528 ,  H01L29/78 ,  H01L29/66 ,  H01L27/11 ,  H01L27/092

Abstract: A first S/D region includes a first P-type region, a first N-type region, and a first conductive layer thereon to define a first cell node. A second S/D region includes a second P-type region, a second N-type region, and a second conductive layer thereon to define a second cell node. A PDL transistor and PGLA, PGLB transistors have bottom SD regions in the first N-type region. A PUL transistor has a bottom SD region positioned in the first P-type region. A PDR transistor and PGRA, PGRB have bottom SD regions in the second N-type region. A PUR transistor has a bottom SD region in the second P-type region. A first gate is positioned around channel regions of the PUL and PDL transistors and conductively coupled to the second node. A second gate is positioned around channel regions of the PUR and PDR transistors and conductively coupled to the first node.

公开(公告)号：US10418368B1

公开(公告)日：2019-09-17

申请号：US16031030

申请日：2018-07-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven J. Bentley ,  Bipul C. Paul ,  Steven R. Soss

IPC: H01L27/11 ,  H01L23/528 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/768 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08

Abstract: A method for forming a buried local interconnect in a source/drain region is disclosed including, among other things, forming a plurality of VOC structures, forming a first source/drain region between a first pair of the plurality of VOC structures, forming a second source/drain region between a second pair of the plurality of VOC structures, and forming an isolation structure between the first and second source/drain regions. A first trench is formed in the first and second source/drain regions and the isolation structure. A liner layer is formed in the first trench, and a first conductive line is formed in the first trench. A dielectric material is formed above the first conductive line. A first opening is formed in the dielectric material to expose a portion of the first conductive line. A first conductive feature is formed in the first opening contacting the exposed portion of the first conductive line.

公开(公告)号：US20190139967A1

公开(公告)日：2019-05-09

申请号：US15804556

申请日：2017-11-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Randy W. Mann ,  Bipul C. Paul

IPC: H01L27/11 ,  G11C11/412 ,  H01L27/092

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L27/092 ,  H01L2027/11816

Abstract: One illustrative 6T SRAM cell structure disclosed herein includes a first active region with a first N-type pass gate transistor, a first N-type pull-down transistor and a first P-type pull-up transistor, each of which are formed in and above the first active region, wherein the first N-type pull-down transistor is positioned laterally between the first N-type pass gate transistor and the first P-type pull-up transistor, and a second active region with a second N-type pass gate transistor, a second N-type pull-down transistor and a second P-type pull-up transistor, each of which are formed in and above the second active region, wherein the second N-type pull-down transistor is positioned laterally between the second N-type pass gate transistor and the second P-type pull-up transistor.

公开(公告)号：US09761662B1

公开(公告)日：2017-09-12

申请号：US15423647

申请日：2017-02-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bipul C. Paul ,  Kwan-Yong Lim

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/11 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L27/1108 ,  H01L21/823814 ,  H01L21/823885

Abstract: Methods form structures to include a first pair of complementary transistors (having first and second transistors) and a second pair of complementary transistors (having third and fourth transistors). An active area of the first transistor contacts an active area of the second transistor along a first common edge that is straight, and an active area of the third transistor contacts an active area of the fourth transistor along a second common edge that is straight and parallel to the first common edge. The active area of the second transistor has a third edge, opposite the first common edge, that has a non-linear shape, and the active area of the third transistor has a fourth edge, opposite the second common edge, that has the same non-linear shape. The non-linear shape of the third edge faces and is inverted relative to the non-linear shape of the fourth edge.

公开(公告)号：US09202552B2

公开(公告)日：2015-12-01

申请号：US14105939

申请日：2013-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bipul C. Paul ,  Randy W. Mann ,  Sangmoon J. Kim

IPC: G11C11/00 ,  G11C11/412 ,  G11C8/16

CPC classification number: G11C11/412 ,  G11C8/16 ,  H01L27/0207 ,  H01L27/1104

Abstract: Dual port static random access memory (SRAM) bitcell structures with improve symmetry in access transistors physical placement are provided. The bitcell structures may include, for example, two pairs of parallel pull-down transistors. The bitcell structures may also include pass-gate transistors PGLA and PGRA forming a first port, and pass-gate transistors PGLB and PGRB forming a second port. The pass-gate transistors PGLA and PGLB may be adjacent one another and a first side of the bitcell structure, and pass-gate transistors PGRA and PGRB may be adjacent one another and a second side of the bitcell structure. Each of the pass-gate transistors PGLA and PGLB may be connected with one of the pull-down transistors of one of the pairs of parallel pull-down transistors. Similarly, each of the pass-gate transistors PGRA and PGRB may be connected with one of the pull-down transistors of the other pair of parallel pull-down transistors.

Abstract translation: 提供了具有提高存取晶体管物理放置对称性的双端口静态随机存取存储器（SRAM）位单元结构。 比特单元结构可以包括例如两对并行下拉晶体管。 比特单元结构还可以包括形成第一端口的通过栅极晶体管PGLA和PGRA，以及形成第二端口的通过栅极晶体管PGLB和PGRB。 通路栅极晶体管PGLA和PGLB可以彼此相邻，并且位单元结构的第一侧，以及栅极晶体管PGRA和PGRB可以彼此相邻，并且位单元结构的第二侧。 每个通栅晶体管PGLA和PGLB可以与一对并联下拉晶体管中的一个的下拉晶体管中的一个连接。 类似地，每个通栅晶体管PGRA和PGRB可以与另一对并联下拉晶体管的下拉晶体管中的一个连接。

公开(公告)号：US08751985B1

公开(公告)日：2014-06-10

申请号：US13795198

申请日：2013-03-12

Applicant: Globalfoundries Inc.

Inventor： Sandeep Puri ,  Bipul C. Paul ,  Werner Juengling ,  Anurag Mittal

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: Hierarchical layout versus schematic comparison with extraneous device elimination is provided. This includes obtaining a hierarchical layout netlist for a circuit design, the hierarchical layout netlist grouping arrayed devices of the circuit design into blocks repeated at a top level of a hierarchy of the hierarchical layout netlist. A modified hierarchical layout netlist defining active devices and connections thereof to top level pads of the circuit design is generated, in which extraneous devices are selectively removed from the obtained hierarchical layout netlist. The modified hierarchical layout netlist is verified against an input schematic netlist defining active devices of the circuit design and connections thereof to pads of the circuit design.

Abstract translation: 提供了层次布局与与外部设备消除的原理图比较。 这包括获得用于电路设计的分层布局网表，分层布局网表将电路设计的阵列设备分组成在分级布局网表的层次结构的顶层重复的块。 产生了将有源器件及其连接定义为电路设计的顶级焊盘的修改的分层布局网表，其中从获得的分层布局网表中选择性地移除了外来设备。 修改的分层布局网表针对定义电路设计的有源器件的输入原理图网表及其与电路设计的焊盘的连接来验证。

公开(公告)号：US20200286900A1

公开(公告)日：2020-09-10

申请号：US16295485

申请日：2019-03-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Randy W. Mann ,  Bipul C. Paul ,  Julien Frougier ,  Ruilong Xie

IPC: H01L27/11 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

Abstract: Structures and static random access memory bit cells including complementary field effect transistors and methods of forming such structures and bit cells. A first complementary field-effect transistor has a first storage nanosheet transistor, a second storage nanosheet transistor stacked over the first storage nanosheet transistor, and a first gate electrode shared by the first storage nanosheet transistor and the second storage nanosheet transistor. A second complementary field-effect transistor has a third storage nanosheet transistor, a fourth storage nanosheet transistor stacked over the third storage nanosheet transistor, and a second gate electrode shared by the third storage nanosheet transistor and the fourth storage nanosheet transistor. The first gate electrode and the second gate electrode are arranged in a spaced arrangement along a longitudinal axis. All gate electrodes of the SRAM bitcell may be arranged in a 1CPP layout.

公开(公告)号：US10651284B2

公开(公告)日：2020-05-12

申请号：US15791650

申请日：2017-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088

Abstract: One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.

公开(公告)号：US20190355730A1

公开(公告)日：2019-11-21

申请号：US15983627

申请日：2018-05-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Randy W. Mann ,  Bipul C. Paul

IPC: H01L27/11

Abstract: Structures for a static random access memory (SRAM) bitcell and methods for forming a SRAM bitcell. The SRAM includes a storage element with a first pull-up (PU) vertical-transport field-effect transistor (VTFET) having a first bottom source/drain region and a fin projecting from the first bottom source/drain region, and a second pull-up (PU) VTFET with a second bottom source/drain region and a fin projecting from the second bottom source/drain region. The fin of the first PU VTFET is arranged over a first active region in which the first bottom source/drain region is centrally arranged, and the fin of the second PU VTFET is arranged over a second active region in which the second bottom source/drain region is centrally arranged. The second source/drain region is aligned with the first bottom source/drain region. A read port may be connected with the storage element, and may also be formed using VTFETs.

公开(公告)号：US10403629B2

公开(公告)日：2019-09-03

申请号：US15804556

申请日：2017-11-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Randy W. Mann ,  Bipul C. Paul

IPC: H01L27/11 ,  H01L27/092 ,  G11C11/412 ,  H01L27/118

Abstract: One illustrative 6T SRAM cell structure disclosed herein includes a first active region with a first N-type pass gate transistor, a first N-type pull-down transistor and a first P-type pull-up transistor, each of which are formed in and above the first active region, wherein the first N-type pull-down transistor is positioned laterally between the first N-type pass gate transistor and the first P-type pull-up transistor, and a second active region with a second N-type pass gate transistor, a second N-type pull-down transistor and a second P-type pull-up transistor, each of which are formed in and above the second active region, wherein the second N-type pull-down transistor is positioned laterally between the second N-type pass gate transistor and the second P-type pull-up transistor.