公开(公告)号：US10651291B2

公开(公告)日：2020-05-12

申请号：US15680467

申请日：2017-08-18

申请人： GLOBALFOUNDRIES Inc.

发明人： Julien Frougier ,  Ruilong Xie

IPC分类号： H01L29/20 ,  H01L29/16 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L21/223 ,  H01L21/311 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/786

摘要： Structures for a nanosheet field-effect transistor and methods for forming a structure for a nanosheet field-effect transistor. A body feature is formed that includes a sacrificial layer arranged vertically between the first and second nanosheet channel layers. The sacrificial layer is laterally recessed at a sidewall of the body feature to expose respective portions of the first and second nanosheet channel layers. A sacrificial spacer is formed by oxidizing a portion of the sacrificial layer at the sidewall of the body feature. Sections of a semiconductor material are epitaxially grown on the exposed portions of the first and second nanosheet channel layers to narrow a gap vertically separating the first and second nanosheet channel layers. The sacrificial spacer is removed to form a cavity between the sections of the semiconductor material and the sacrificial layer. A dielectric spacer is conformally deposited in the cavity.

公开(公告)号：US20190341448A1

公开(公告)日：2019-11-07

申请号：US15968968

申请日：2018-05-02

申请人： GLOBALFOUNDRIES INC.

发明人： Emilie M.S. Bourjot ,  Julien Frougier ,  Yi Qi ,  Ruilong Xie ,  Hui Zang ,  Hsien-Ching Lo ,  Zhenyu Hu

IPC分类号： H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66 ,  H01L29/08

摘要： Various aspects of the disclosure include nanosheet-FET structures having a wrap-all-around contact where the contact wraps entirely around the S/D epitaxy structure, not just on the top and sides of the S/D epitaxy structure, thereby increasing contact area and ultimately allowing for improved S/D contact resistance. Other aspects of the disclosure include nanosheet-FET structures having a bottom isolation to reduce parasitic S/D leakage to the substrate.

公开(公告)号：US20190287863A1

公开(公告)日：2019-09-19

申请号：US15920748

申请日：2018-03-14

申请人： GLOBALFOUNDRIES INC.

发明人： Ruilong Xie ,  Lars Liebmann ,  Edward J. Nowak ,  Julien Frougier ,  Jia Zeng

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02

摘要： Disclosed is a semiconductor structure that includes a vertical field effect transistor (VFET) with a U-shaped semiconductor body. The semiconductor structure can be a standard VFET or a feedback VFET. In either case, the VFET includes a lower source/drain region, a semiconductor body on the lower source/drain region, and an upper source/drain region on the top of the semiconductor body. Rather than having an elongated fin shape, the semiconductor body folds back on itself in the Z direction so as to be essentially U-shaped (as viewed from above). Using a U-shaped semiconductor body reduces the dimension of the VFET in the Z direction without reducing the end-to-end length of the semiconductor body. Thus, VFET cell height can be reduced without reducing device drive current or violating critical design rules. Also disclosed is a method of forming a semiconductor structure that includes such a VFET with a U-shaped semiconductor body.

公开(公告)号：US10290549B2

公开(公告)日：2019-05-14

申请号：US15695229

申请日：2017-09-05

申请人： GLOBALFOUNDRIES INC.

发明人： Ruilong Xie ,  Julien Frougier ,  Min Gyu Sung ,  Edward Joseph Nowak ,  Nigel G. Cave ,  Lars Liebmann ,  Daniel Chanemougame ,  Andreas Knorr

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L27/11

摘要： The disclosure is directed to gate all-around integrated circuit structures, finFETs having a dielectric isolation, and methods of forming the same. The gate all-around integrated circuit structure may include a first insulator region within a substrate; a pair of remnant liner stubs disposed within the first insulator region; a second insulator region laterally adjacent to the first insulator region within the substrate; a pair of fins over the first insulator region, each fin in the pair of fins including an inner sidewall facing the inner sidewall of an adjacent fin in the pair of fins and an outer sidewall opposite the inner sidewall; and a gate structure substantially surrounding an axial portion of the pair of fins and at least partially disposed over the first and second insulator regions, wherein each remnant liner stub is substantially aligned with the inner sidewall of a respective fin of the pair of fins.

公开(公告)号：US20190123160A1

公开(公告)日：2019-04-25

申请号：US16190549

申请日：2018-11-14

申请人： GLOBALFOUNDRIES INC.

发明人： Ruilong Xie ,  Andreas Knorr ,  Julien Frougier ,  Hui Zang ,  Min-hwa Chi

IPC分类号： H01L29/423 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L29/49 ,  H01L29/786

摘要： A method of forming a GAA FinFET, including: forming a fin on a substrate, the substrate having a STI layer formed thereon and around a portion of a FIN-bottom portion of the fin, the fin having a dummy gate formed thereover, the dummy gate having a gate sidewall spacer on sidewalls thereof; forming a FIN-void and an under-FIN cavity in the STI layer; forming first spacers by filling the under-FIN cavity and FIN-void with a first fill; removing the dummy gate, thereby exposing both FIN-bottom and FIN-top portions of the fin underneath the gate; creating an open area underneath the exposed FIN-top by removing the exposed FIN-bottom; and forming a second spacer by filling the open area with a second fill; wherein a distance separates a top-most surface of the second spacer from a bottom-most surface of the FIN-top portion. A GAA FinFET formed by the method is also disclosed.

公开(公告)号：US10164041B1

公开(公告)日：2018-12-25

申请号：US15790216

申请日：2017-10-23

申请人： GLOBALFOUNDRIES INC.

发明人： Ruilong Xie ,  Andreas Knorr ,  Julien Frougier ,  Hui Zang ,  Min-hwa Chi

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/49 ,  H01L29/786 ,  H01L27/088

摘要： A method of forming a GAA FinFET, including: forming a fin on a substrate, the substrate having a STI layer formed thereon and around a portion of a FIN-bottom portion of the fin, the fin having a dummy gate formed thereover, the dummy gate having a gate sidewall spacer on sidewalls thereof; forming a FIN-void and an under-FIN cavity in the STI layer; forming first spacers by filling the under-FIN cavity and FIN-void with a first fill; removing the dummy gate, thereby exposing both FIN-bottom and FIN-top portions of the fin underneath the gate; creating an open area underneath the exposed FIN-top by removing the exposed FIN-bottom; and forming a second spacer by filling the open area with a second fill; wherein a distance separates a top-most surface of the second spacer from a bottom-most surface of the FIN-top portion. A GAA FinFET formed by the method is also disclosed.

公开(公告)号：US09991352B1

公开(公告)日：2018-06-05

申请号：US15651282

申请日：2017-07-17

申请人： GLOBALFOUNDRIES Inc.

发明人： Julien Frougier ,  Ali Razavieh ,  Ruilong Xie ,  Steven Bentley

IPC分类号： H01L29/76 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC分类号： H01L29/42364 ,  H01L29/0665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785

摘要： A method that includes forming a patterned stack of materials comprising at least one channel semiconductor material layer and first and second layers of sacrificial material positioned above and below, respectively, the at least one channel semiconductor material layer, forming a replacement gate cavity above the patterned stack of materials and performing an etching process through the gate cavity to selectively remove at least a portion of the first and second layers of sacrificial material relative to the at least one channel semiconductor material layer. The method further includes performing a second etching process to form a reduced-thickness portion of the channel semiconductor material layer that has a final thickness that is less than the initial thickness and forming a replacement gate structure around at least the reduced-thickness portion of the channel semiconductor material layer.

公开(公告)号：US20210043727A1

公开(公告)日：2021-02-11

申请号：US16534317

申请日：2019-08-07

申请人： GLOBALFOUNDRIES INC.

发明人： Julien Frougier ,  Ruilong Xie ,  Kangguo Cheng ,  Chanro Park

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66

摘要： A gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes nanosheets, a gate around center portions of the nanosheets, and inner spacers aligned below end portions. The nanosheet end portions are tapered from the source/drain regions to the gate and the inner spacers are tapered from the gate to the source/drain regions. Each inner spacer includes: a first spacer layer, which has a uniform thickness and extends laterally from the gate to an adjacent source/drain region; a second spacer layer, which fills the space between a planar top surface of the first spacer layer and a tapered end portion of the nanosheet above; and, for all but the lowermost inner spacers, a third spacer layer, which is the same material as the second spacer layer and which fills the space between a planar bottom surface of the first spacer layer and a tapered end portion of the nanosheet below.

公开(公告)号：US10818803B1

公开(公告)日：2020-10-27

申请号：US16516623

申请日：2019-07-19

申请人： GLOBALFOUNDRIES Inc.

发明人： Julien Frougier ,  Ali Razavieh

IPC分类号： H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L29/786 ,  H01L29/10 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/16

摘要： Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A source/drain region is connected with a channel layer, and a gate structure extends across the channel layer. The channel layer is composed of a two-dimensional material.

公开(公告)号：US10804398B2

公开(公告)日：2020-10-13

申请号：US16160701

申请日：2018-10-15

申请人： GLOBALFOUNDRIES Inc.

发明人： Julien Frougier ,  Ruilong Xie

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/66

摘要： A device including source-drain epitaxy contacts with a trench silicide (TS) liner wrapped around the source-drain contacts, and method of production thereof. Embodiments include a device having a gate structure formed over a substrate; source-drain epitaxy contacts including a trench silicide (TS) liner covering the source-drain epitaxy contacts; TS contacts formed on the TS liner over the source-drain epitaxy contacts; and a dielectric pillar disposed in a TS cut between the source-drain epitaxy contacts. The TS liner wraps around the source-drain epitaxy contacts, including bottom negatively tapered surfaces of the source-drain epitaxy contacts.