公开(公告)号：US20160246167A1

公开(公告)日：2016-08-25

申请号：US14628446

申请日：2015-02-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Amr Y. Abdo ,  Nathalie Casati ,  Maria Gabrani ,  James M. Oberschmidt ,  Ramya Viswanathan ,  Josef S. Watts

IPC: G03F1/36 ,  G06F17/50

CPC classification number: G03F1/36 ,  G06F17/5081

Abstract: Methods, program products, and systems for improving optical proximity correction (OPC) calibration, and automatically determining a minimal number of clips, are disclosed. The method can include using a computing device to perform actions including: calculating a total relevancy score for a projected sample plan including a candidate clip, and wherein the relevancy score is derived from at least one relevancy criterion and a relevancy weight; calculating a relevancy score for the candidate clip, the relevancy score for the candidate clip being a contribution from the candidate clip to the total relevancy score; and adding the candidate clip to a sample plan for the IC layout and removing the candidate clip from the plurality of clips in response a difference in relevancy score between the projected sample plan and one or more previous sample plans substantially fitting a non-linear relevancy score function.

Abstract translation: 公开了用于改进光学邻近校正（OPC）校准以及自动确定最小数量的片段的方法，程序产品和系统。 该方法可以包括使用计算设备来执行动作，包括：计算包括候选剪辑的投影样本计划的总相关性得分，并且其中所述相关性得分来自至少一个相关性标准和相关权重; 计算候选剪辑的相关性分数，候选剪辑的相关性分数是从候选剪辑到总相关性分数的贡献; 以及将所述候选剪辑添加到所述IC布局的样本计划并从所述多个剪辑中移除所述候选剪辑，以响应所述预测样本计划与基本拟合非线性相关性得分的一个或多个先前样本计划之间的相关性得分的差异 功能。

公开(公告)号：US20180122891A1

公开(公告)日：2018-05-03

申请号：US15848324

申请日：2017-12-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Josef S. Watts ,  Shesh M. Pandey

IPC: H01L49/02 ,  H01L27/06 ,  H01L21/02 ,  H01L21/3205

CPC classification number: H01L28/20 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02595 ,  H01L21/32055 ,  H01L27/0629

Abstract: A resistor body is separated from a doped well in a substrate by a resistor dielectric material layer. The doped well is defined by at least one doped region and can include a dopant gradient in the doped well to reduce parasitic capacitance of the resistor structure while retaining heat dissipation properties of the substrate. The resistor body is formed in a cavity in a dielectric layer deposited on the substrate, which deposition can be part of a concurrent fabrication, such as part of forming shallow trench isolations, and the cavity can be lined with the resistor dielectric material.

公开(公告)号：US09923046B1

公开(公告)日：2018-03-20

申请号：US15271730

申请日：2016-09-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Josef S. Watts ,  Shesh M. Pandey

IPC: H01L49/02 ,  H01L21/3205 ,  H01L21/02 ,  H01L27/06

CPC classification number: H01L28/20 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02595 ,  H01L21/32055 ,  H01L27/0629

Abstract: A resistor body is separated from a doped well in a substrate by a resistor dielectric material layer. The doped well is defined by at least one doped region and can include a dopant gradient in the doped well to reduce parasitic capacitance of the resistor structure while retaining heat dissipation properties of the substrate. The resistor body is formed in a cavity in a dielectric layer deposited on the substrate, which deposition can be part of a concurrent fabrication, such as part of forming shallow trench isolations, and the cavity can be lined with the resistor dielectric material.

公开(公告)号：US09704763B2

公开(公告)日：2017-07-11

申请号：US14146143

申请日：2014-01-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Amit A. Dikshit ,  Tamilmani Ethirajan ,  Shrinivas J. Pandharpure ,  Vaidyanathan T. Subramanian ,  Josef S. Watts

IPC: H01L21/84 ,  H01L21/66 ,  G06F17/50 ,  G01R31/26

CPC classification number: H01L22/14 ,  G01R31/2621 ,  G01R31/2625 ,  G06F17/5036 ,  G06F17/5063

Abstract: Various embodiments include approaches for predicting unity gain frequency in a MOSFET. In some cases, a method includes predicting a unity gain frequency (fT) in a MOSFET device in a manufacturing line, the method including: measuring a first set of in-line direct current (DC) parameters of the MOSFET on the manufacturing line at a first drain voltage (Vd1); extracting a transconductance (Gm) from the first set of in-line DC parameters as a function of a gate-voltage (Vg) and the first drain-voltage (Vd1); measuring a second set of in-line DC parameters of the MOSFET on the manufacturing line at a second drain voltage (Vd2); extracting a total gate capacitance (Cgg) from the second set of in-line DC parameters as a function of the gate-voltage (Vg); and predicting the unity gain frequency (fT) of the MOSFET based upon the extracted transconductance (Gm) and the extracted total gate capacitance (Cgg).