公开(公告)号：US09960226B2

公开(公告)日：2018-05-01

申请号：US15661504

申请日：2017-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wai-Kin Li ,  Chengwen Pei ,  Ping-Chuan Wang

IPC: H01L49/02 ,  H01L21/8238 ,  H01L27/06

CPC classification number: H01L28/92 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0629

Abstract: High density capacitor structures based on an array of semiconductor nanorods are provided. The high density capacitor structure can be a plurality of capacitors in which each of the semiconductor nanorods serves as a bottom electrode for one of the plurality of capacitors, or a large-area metal-insulator-metal (MIM) capacitor in which the semiconductor nanorods serve as a support structure for a bottom electrode of the MIM capacitor subsequently formed.

公开(公告)号：US20170323937A1

公开(公告)日：2017-11-09

申请号：US15661504

申请日：2017-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wai-Kin Li ,  Chengwen Pei ,  Ping-Chuan Wang

IPC: H01L49/02 ,  H01L21/8238 ,  H01L27/06

CPC classification number: H01L28/92 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0629

Abstract: High density capacitor structures based on an array of semiconductor nanorods are provided. The high density capacitor structure can be a plurality of capacitors in which each of the semiconductor nanorods serves as a bottom electrode for one of the plurality of capacitors, or a large-area metal-insulator-metal (MIM) capacitor in which the semiconductor nanorods serve as a support structure for a bottom electrode of the MIM capacitor subsequently formed.

公开(公告)号：US09666582B1

公开(公告)日：2017-05-30

申请号：US15230632

申请日：2016-08-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wai-Kin Li ,  Chengwen Pei

IPC: H01L21/8232 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/08 ,  H01L23/00

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L23/573 ,  H01L23/576 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/785

Abstract: Devices and methods are provided for constructing a semiconductor structure that implements a PUF (physical unclonable function) based on a FinFET structure. The PUF is based on a random pattern of merged and non-merged source and drain structures, which are formed on adjacent semiconductor fin structures of adjacent pairs of FinFET devices, as a result of process-induced variations in the epitaxial growth of source and drain structures on the semiconductor fin structures. The random pattern of merged and non-merged source and drain structures provides a random pattern of electrical open and short connections between pairs of semiconductor fin structures, wherein the random pattern of electrical open and short connections defines the physical unclonable function.

公开(公告)号：US09576914B2

公开(公告)日：2017-02-21

申请号：US14707442

申请日：2015-05-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wai-Kin Li ,  Chengwen Pei ,  Ping-Chuan Wang

IPC: H01L27/088 ,  H01L23/00 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L27/02

CPC classification number: H01L23/576 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/66537 ,  H01L29/78

Abstract: A Physical Unclonable Function (PUF) semiconductor device includes a semiconductor substrate, and regions, with implant regions and covered regions, in the semiconductor substrate. A hardmask covers a first covered region and a second covered. The first implant region having a first concentration of ions, and at least one second implant region having a second concentration that is less than the first concentration. First and second FETs are formed on the regions. The first and second FETs have a voltage threshold mismatch with respect to one another based on the first region and the at least one second region.

Abstract translation: 物理不可克隆功能（PUF）半导体器件包括半导体衬底，以及在半导体衬底中具有注入区域和覆盖区域的区域。 硬掩模覆盖了第一个覆盖区域，第二个覆盖区域。 具有第一离子浓度的第一植入区域和具有小于第一浓度的第二浓度的至少一个第二植入区域。 在这些区域上形成第一和第二FET。 第一和第二FET基于第一区域和至少一个第二区域相对于彼此具有电压阈值失配。

公开(公告)号：US20160329287A1

公开(公告)日：2016-11-10

申请号：US14707442

申请日：2015-05-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wai-Kin Li ,  Chengwen Pei ,  Ping-Chuan Wang

IPC: H01L23/00 ,  H01L27/02 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L23/576 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/66537 ,  H01L29/78

Abstract: A Physical Unclonable Function (PUF) semiconductor device includes a semiconductor substrate, and regions, with implant regions and covered regions, in the semiconductor substrate. A hardmask covers a first covered region and a second covered. The first implant region having a first concentration of ions, and at least one second implant region having a second concentration that is less than the first concentration. First and second FETs are formed on the regions. The first and second FETs have a voltage threshold mismatch with respect to one another based on the first region and the at least one second region.

Abstract translation: 物理不可克隆功能（PUF）半导体器件包括半导体衬底，以及在半导体衬底中具有注入区域和覆盖区域的区域。 硬掩模覆盖了第一个覆盖区域，第二个覆盖区域。 具有第一离子浓度的第一植入区域和具有小于第一浓度的第二浓度的至少一个第二植入区域。 在这些区域上形成第一和第二FET。 第一和第二FET基于第一区域和至少一个第二区域相对于彼此具有电压阈值失配。

公开(公告)号：US20160247716A1

公开(公告)日：2016-08-25

申请号：US15146510

申请日：2016-05-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Junjing Bao ,  Wai-Kin Li

IPC: H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/7684

Abstract: A dielectric material stack including at least a via level dielectric material layer, at least one patterned etch stop dielectric material portion, a line level dielectric material layer, and optionally a dielectric cap layer is formed over a substrate. At least one patterned hard mask layer including a first pattern can be formed above the dielectric material stack. A second pattern is transferred through the line level dielectric material layer employing the at least one etch stop dielectric material portion as an etch stop structure. The first pattern is transferred through the line level dielectric material layer employing the at least one etch stop dielectric material portion as an etch stop structure while the second pattern is transferred through the via level dielectric material layer to form integrated line and via trenches, which are filled with a conductive material to form integrated line and via structures.

Abstract translation: 包括至少一个通孔级电介质材料层，至少一个图案化的蚀刻停止介电材料部分，一行电介质材料层和任选的电介质盖层的电介质材料堆叠在衬底上。 包括第一图案的至少一个图案化的硬掩模层可以形成在介电材料堆叠的上方。 使用至少一个蚀刻停止介电材料部分作为蚀刻停止结构，通过线路电介质材料层转移第二图案。 第一图案通过采用至少一个蚀刻停止介电材料部分的线路电介质材料层转移作为蚀刻停止结构，而第二图案通过通孔级电介质材料层转移以形成集成线和通孔沟槽， 填充导电材料以形成集成线路和通孔结构。

公开(公告)号：US09337082B2

公开(公告)日：2016-05-10

申请号：US13744756

申请日：2013-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Junjing Bao ,  Wai-Kin Li

IPC: H01L23/48 ,  H01L21/336 ,  H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/7684

Abstract: A dielectric material stack including at least a via level dielectric material layer, at least one patterned etch stop dielectric material portion, a line level dielectric material layer, and optionally a dielectric cap layer is formed over a substrate. At least one patterned hard mask layer including a first pattern can be formed above the dielectric material stack. A second pattern is transferred through the line level dielectric material layer employing the at least one etch stop dielectric material portion as an etch stop structure. The first pattern is transferred through the line level dielectric material layer employing the at least one etch stop dielectric material portion as an etch stop structure while the second pattern is transferred through the via level dielectric material layer to form integrated line and via trenches, which are filled with a conductive material to form integrated line and via structures.

Abstract translation: 包括至少一个通孔级电介质材料层，至少一个图案化的蚀刻停止介电材料部分，一行电介质材料层和任选的电介质盖层的电介质材料堆叠在衬底上。 包括第一图案的至少一个图案化的硬掩模层可以形成在介电材料堆叠的上方。 使用至少一个蚀刻停止介电材料部分作为蚀刻停止结构，通过线路电介质材料层转移第二图案。 第一图案通过采用至少一个蚀刻停止介电材料部分的线路电介质材料层转移作为蚀刻停止结构，而第二图案通过通孔级电介质材料层转移以形成集成线和通孔沟槽， 填充导电材料以形成集成线路和通孔结构。