公开(公告)号：US20160268400A1

公开(公告)日：2016-09-15

申请号：US14656671

申请日：2015-03-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem AKARVARDAR ,  Jody A. FRONHEISER ,  Ajey Poovannummoottil JACOB

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/66795 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66545

Abstract: Commonly fabricated FinFET type semiconductor devices with different (i.e., both taller and shorter) heights of an entirety of or only the channel region of some of the fins. Where only the channel of some of the fins has a different height, the sources and drains have a common height higher than those channels. The different fin heights are created by recessing some of the fins, and where only the channels have different heights, the difference is created by exposing a top surface of each channel intended to be shorter, the other channels being masked, and partially recessing the exposed channel(s). In both cases, the mask(s) may then be removed and conventional FinFET processing may proceed.

Abstract translation: 通常制造的FinFET型半导体器件具有不同（即，较高和较短）高度的整个或仅一些鳍片的沟道区域。 在只有一些翅片的通道具有不同的高度的情况下，源和下水道具有比这些通道高的公共高度。 不同的翅片高度是通过使一些翅片凹陷而产生的，并且只有通道具有不同的高度，差异是通过暴露每个通道的顶表面旨在更短，其他通道被遮蔽并部分地使暴露的 频道。 在这两种情况下，可以去除掩模，并且可以进行常规的FinFET处理。

公开(公告)号：US20160197004A1

公开(公告)日：2016-07-07

申请号：US14590591

申请日：2015-01-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem AKARVARDAR ,  Jody A. FRONHEISER

IPC: H01L21/762 ,  H01L29/10 ,  H01L29/78 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/76202 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, fabricating a semiconductor fin structure by: providing a fin structure extending above a substrate, the fin structure including a first fin portion, a second fin portion disposed over the first fin portion, and an interface between the first and the second fin portions, where the first fin portion and the second fin portion are lattice mismatched within the fin structure; and modifying, in part, the fin structure to obtain a modified fin structure, the modifying including selectively oxidizing the interface to form an isolation region within the modified fin structure, where the isolation region electrically insulates the first fin portion from the second fin portion, while maintaining structural stability of the modified fin structure.

Abstract translation: 提供半导体结构和制造方法，其包括例如通过以下方式制造半导体鳍结构：提供在衬底上延伸的鳍结构，所述鳍结构包括第一鳍部，设置在第一鳍部上方的第二鳍部，以及 所述第一翅片部分和所述第二翅片部分之间的界面，其中所述第一鳍片部分和所述第二鳍片部分在所述鳍片结构内晶格失配; 并且部分地修改所述翅片结构以获得改性翅片结构，所述修改包括选择性地氧化所述界面以在所述改进的翅片结构内形成隔离区域，其中所述隔离区域将所述第一翅片部分与所述第二翅片部分电绝缘， 同时保持改性翅片结构的结构稳定性。

公开(公告)号：US20150061014A1

公开(公告)日：2015-03-05

申请号：US14011125

申请日：2013-08-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil JACOB ,  Murat Kerem AKARVARDAR ,  Steven John BENTLEY ,  Bartlomiej Jan PAWLAK

IPC: H01L21/764 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L21/764 ,  H01L21/02488 ,  H01L21/02587 ,  H01L21/762 ,  H01L29/66795 ,  H01L29/785

Abstract: A first semiconductor structure includes a bulk silicon substrate and one or more original silicon fins coupled to the bulk silicon substrate. A dielectric material is conformally blanketed over the first semiconductor structure and recessed to create a dielectric layer. A first cladding material is deposited adjacent to the original silicon fin, after which the original silicon fin is removed to form a second semiconductor structure having two fins that are electrically isolated from the bulk silicon substrate. A second cladding material is patterned adjacent to the first cladding material to form a third semiconductor structure having four fins that are electrically isolated from the bulk silicon substrate.

Abstract translation: 第一半导体结构包括体硅衬底和耦合到体硅衬底的一个或多个原始硅鳍片。 电介质材料保形地覆盖在第一半导体结构上并凹进以产生电介质层。 第一覆层材料沉积在原始硅鳍片附近，之后去除原始硅片以形成具有与体硅衬底电隔离的两个散热片的第二半导体结构。 第二包层材料被图案化为与第一包层材料相邻以形成具有与体硅衬底电隔离的四个散热片的第三半导体结构。

公开(公告)号：US20150021709A1

公开(公告)日：2015-01-22

申请号：US13945379

申请日：2013-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey P. JACOB ,  Murat Kerem AKARVARDAR ,  Michael John HARGROVE

IPC: H01L27/12 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L27/1211 ,  H01L21/76229 ,  H01L21/76281 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/7848

Abstract: Semiconductor structures and fabrication methods are provided integrating different fin device architectures on a common wafer, for instance, within a common functional device area of the wafer. The method includes: facilitating fabricating multiple fin device architectures within a common functional device wafer area by: providing a wafer with at least one fin disposed over a substrate, the fin including an isolation layer; modifying the fin(s) in a first region of the fin(s), while protecting the fin in a second region of the fin(s); and proceeding with forming one or more fin devices of a first architectural type in the first region and one or more fin devices of a second architectural type in the second region. The first architectural type and the second architectural type are different fin device architectures, such as different fin device isolation architectures, different fin type transistor architectures, or different fin-type devices or structures.

Abstract translation: 提供半导体结构和制造方法，其在公共晶片上集成了不同的鳍式器件结构，例如在晶片的公共功能器件区域内。 该方法包括：通过以下方式促进在公共功能器件晶片区域内制造多个鳍器件结构：提供具有设置在衬底上的至少一个鳍的晶片，所述鳍包括隔离层; 在翅片的第一区域中修改翅片，同时保护翅片的第二区域中的翅片; 并且继续在第一区域中形成第一建筑类型的一个或多个翅片装置和在第二区域中形成第二建筑类型的一个或多个翅片装置。 第一种架构类型和第二种结构类型是不同的鳍式器件架构，例如不同的鳍式器件隔离架构，不同鳍型晶体管架构，或不同鳍型器件或结构。