公开(公告)号：US20150021691A1

公开(公告)日：2015-01-22

申请号：US13945455

申请日：2013-07-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Murat Kerem AKARVARDAR ,  Jody A. FRONHEISER ,  Ajey Poovannummoottil JACOB

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L29/66795

Abstract: A semiconductor stack of a FinFET in fabrication includes a bulk silicon substrate, a selectively oxidizable sacrificial layer over the bulk substrate and an active silicon layer over the sacrificial layer. Fins are etched out of the stack of active layer, sacrificial layer and bulk silicon. A conformal oxide deposition is made to encapsulate the fins, for example, using a HARP deposition. Relying on the sacrificial layer having a comparatively much higher oxidation rate than the active layer or substrate, selective oxidization of the sacrificial layer is performed, for example, by annealing. The presence of the conformal oxide provides structural stability to the fins, and prevents fin tilting, during oxidation. Selective oxidation of the sacrificial layer provides electrical isolation of the top active silicon layer from the bulk silicon portion of the fin, resulting in an SOI-like structure. Further fabrication may then proceed to convert the active layer to the source, drain and channel of the FinFET. The oxidized sacrificial layer under the active channel prevents punch-through leakage in the final FinFET structure.

Abstract translation: FinFET的半导体堆叠制造包括体硅衬底，在主体衬底上的可选择性氧化的牺牲层和牺牲层上的活性硅层。 翅片从有源层，牺牲层和体硅的堆叠中蚀刻出来。 制造保形氧化物沉积来封装散热片，例如使用HARP沉积。 依靠具有比有源层或衬底高得多的氧化速率的牺牲层，例如通过退火进行牺牲层的选择性氧化。 保形氧化物的存在为翅片提供结构稳定性，并防止在氧化过程中翅片的倾斜。 牺牲层的选择性氧化提供顶部有源硅层与散热片的体硅部分的电隔离，导致类SOI结构。 然后进一步制造可以将有源层转换成FinFET的源极，漏极和沟道。 有源通道下方的氧化牺牲层可防止最终的FinFET结构中的穿透泄漏。

公开(公告)号：US20180226505A1

公开(公告)日：2018-08-09

申请号：US15424379

申请日：2017-02-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiseok KIM ,  Hiroaki NIIMI ,  Hoon KIM ,  Puneet Harischandra SUVARNA ,  Steven BENTLEY ,  Jody A. FRONHEISER

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/36

CPC classification number: H01L29/7827 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78642

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical transport field effect transistor devices and methods of manufacture. A structure includes: a vertical fin structure having a lower dopant region, an upper dopant region and a channel region between the lower dopant region and the upper dopant region; and a doped semiconductor material provided on sides of the vertical fin structure at a lower portion. The lower dopant region being composed of the doped semiconductor material which is merged into the vertical fin structure at the lower portion.

公开(公告)号：US20180138079A1

公开(公告)日：2018-05-17

申请号：US15848371

申请日：2017-12-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem AKARVARDAR ,  Jody A. FRONHEISER

IPC: H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/04

CPC classification number: H01L21/76202 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, fabricating a semiconductor fin structure by: providing a fin structure extending above a substrate, the fin structure including a first fin portion, a second fin portion disposed over the first fin portion, and an interface between the first and the second fin portions, where the first fin portion and the second fin portion are lattice mismatched within the fin structure; and modifying, in part, the fin structure to obtain a modified fin structure, the modifying including selectively oxidizing the interface to form an isolation region within the modified fin structure, where the isolation region electrically insulates the first fin portion from the second fin portion, while maintaining structural stability of the modified fin structure.

公开(公告)号：US20160343806A1

公开(公告)日：2016-11-24

申请号：US14718402

申请日：2015-05-21

Applicant: GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  LAM RESEARCH CORPORATION

Inventor： Shariq SIDDIQUI ,  Jody A. FRONHEISER ,  Murat Kerem AKARVARDAR ,  Purushothaman SRINIVASAN ,  Lisa F. EDGE ,  Gangadhara Raja MUTHINTI ,  Georges JACOBI ,  Randolph KNARR

IPC: H01L29/161 ,  H01L29/51 ,  H01L29/423 ,  H01L29/66 ,  H01L23/29 ,  H01L23/31 ,  H01L21/311 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/161 ,  H01L21/0206 ,  H01L21/02175 ,  H01L21/02236 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/28255 ,  H01L21/31111 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/78

Abstract: Methods for fabricating interface passivation layers in a circuit structure are provided. The method includes forming a silicon-germanium layer over a substrate, removing a native oxide layer from an upper surface of the silicon-germanium layer, and exposing the upper surface of the silicon-germanium layer to an ozone-containing solution, resulting in an interface passivation layer with a higher concentration of germanium-dioxide present than germanium-oxide. The resulting interface passivation layer may be part of a gate structure, in which the channel region of the gate structure includes the silicon-germanium layer and the interface passivation layer between the channel region and the dielectric layer of the gate structure has a high concentration of germanium-dioxide.

Abstract translation: 提供了一种在电路结构中制造界面钝化层的方法。 该方法包括在衬底上形成硅锗层，从硅 - 锗层的上表面去除自然氧化物层，并将硅 - 锗层的上表面暴露于含臭氧的溶液中，得到 具有比锗氧化物更高浓度的二氧化锗的界面钝化层。 所得到的界面钝化层可以是栅极结构的一部分，其中栅极结构的沟道区域包括硅 - 锗层，并且沟道区域和栅极结构的电介质层之间的界面钝化层具有高浓度 二氧化锗。

公开(公告)号：US20160005657A1

公开(公告)日：2016-01-07

申请号：US14853537

申请日：2015-09-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bharat KRISHNAN ,  Jody A. FRONHEISER ,  Jinping LIU ,  Bongki LEE

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L21/823431 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/324 ,  H01L29/0657 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor structure includes a bulk silicon substrate and one or more silicon fins coupled to the bulk silicon substrate. Stress-inducing material(s), such as silicon, are epitaxially grown on the fins into naturally diamond-shaped structures using a controlled selective epitaxial growth. The diamond shaped structures are subjected to annealing at about 750° C. to about 850° C. to increase an area of (100) surface orientation by reshaping the shaped structures from the annealing. Additional epitaxial material is grown on the increased (100) area. Multiple cycles of increasing the area of (100) surface orientation (e.g., by the annealing) and growing additional epitaxial material on the increased area are performed to decrease the width of the shaped structures, increasing the space between them to prevent them from merging, while also increasing their volume.

Abstract translation: 半导体结构包括体硅衬底和耦合到体硅衬底的一个或多个硅散热片。 使用受控的选择性外延生长，诸如硅的应力诱导材料在翅片上外延生长成天然的菱形结构。 金刚石结构在约750℃至约850℃下进行退火，以通过从退火中重塑成形结构来增加（100）表面取向的面积。 额外的外延材料在增加的（100）区域上生长。 进行增加（100）表面取向（例如通过退火）的面积和在增加的面积上生长另外的外延材料的多个循环以减小成形结构的宽度，增加它们之间的空间以防止它们的合并， 同时也增加了他们的数量。

公开(公告)号：US20160268400A1

公开(公告)日：2016-09-15

申请号：US14656671

申请日：2015-03-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem AKARVARDAR ,  Jody A. FRONHEISER ,  Ajey Poovannummoottil JACOB

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/66795 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66545

Abstract: Commonly fabricated FinFET type semiconductor devices with different (i.e., both taller and shorter) heights of an entirety of or only the channel region of some of the fins. Where only the channel of some of the fins has a different height, the sources and drains have a common height higher than those channels. The different fin heights are created by recessing some of the fins, and where only the channels have different heights, the difference is created by exposing a top surface of each channel intended to be shorter, the other channels being masked, and partially recessing the exposed channel(s). In both cases, the mask(s) may then be removed and conventional FinFET processing may proceed.

Abstract translation: 通常制造的FinFET型半导体器件具有不同（即，较高和较短）高度的整个或仅一些鳍片的沟道区域。 在只有一些翅片的通道具有不同的高度的情况下，源和下水道具有比这些通道高的公共高度。 不同的翅片高度是通过使一些翅片凹陷而产生的，并且只有通道具有不同的高度，差异是通过暴露每个通道的顶表面旨在更短，其他通道被遮蔽并部分地使暴露的 频道。 在这两种情况下，可以去除掩模，并且可以进行常规的FinFET处理。

公开(公告)号：US20160197004A1

公开(公告)日：2016-07-07

申请号：US14590591

申请日：2015-01-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem AKARVARDAR ,  Jody A. FRONHEISER

IPC: H01L21/762 ,  H01L29/10 ,  H01L29/78 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/76202 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, fabricating a semiconductor fin structure by: providing a fin structure extending above a substrate, the fin structure including a first fin portion, a second fin portion disposed over the first fin portion, and an interface between the first and the second fin portions, where the first fin portion and the second fin portion are lattice mismatched within the fin structure; and modifying, in part, the fin structure to obtain a modified fin structure, the modifying including selectively oxidizing the interface to form an isolation region within the modified fin structure, where the isolation region electrically insulates the first fin portion from the second fin portion, while maintaining structural stability of the modified fin structure.

Abstract translation: 提供半导体结构和制造方法，其包括例如通过以下方式制造半导体鳍结构：提供在衬底上延伸的鳍结构，所述鳍结构包括第一鳍部，设置在第一鳍部上方的第二鳍部，以及 所述第一翅片部分和所述第二翅片部分之间的界面，其中所述第一鳍片部分和所述第二鳍片部分在所述鳍片结构内晶格失配; 并且部分地修改所述翅片结构以获得改性翅片结构，所述修改包括选择性地氧化所述界面以在所述改进的翅片结构内形成隔离区域，其中所述隔离区域将所述第一翅片部分与所述第二翅片部分电绝缘， 同时保持改性翅片结构的结构稳定性。

公开(公告)号：US20150123146A1

公开(公告)日：2015-05-07

申请号：US14071170

申请日：2013-11-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bharat KRISHNAN ,  Jody A. FRONHEISER ,  Jinping LIU ,  Bongki LEE

IPC: H01L21/02 ,  H01L29/165 ,  H01L29/78 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L21/823431 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/324 ,  H01L29/0657 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor structure includes a bulk silicon substrate and one or more silicon fins coupled to the bulk silicon substrate. Stress-inducing material(s), such as silicon, are epitaxially grown on the fins into naturally diamond-shaped structures using a controlled selective epitaxial growth. The diamond shaped structures are subjected to annealing at about 750° C. to about 850° C. to increase an area of (100) surface orientation by reshaping the shaped structures from the annealing. Additional epitaxy is grown on the increased (100) area. Multiple cycles of increasing the area of (100) surface orientation (e.g., by the annealing) and growing additional epitaxy on the increased area are performed to decrease the width of the shaped structures, increasing the space between them to prevent them from merging, while also increasing their volume.

Abstract translation: 半导体结构包括体硅衬底和耦合到体硅衬底的一个或多个硅散热片。 使用受控的选择性外延生长，诸如硅的应力诱导材料在翅片上外延生长成天然的菱形结构。 金刚石结构在约750℃至约850℃下进行退火，以通过从退火中重塑成形结构来增加（100）表面取向的面积。 额外的外延生长在增加的（100）区域。 进行增加（100）表面取向（例如通过退火）的面积和在增加的面积上生长附加外延的多个循环以减小成形结构的宽度，增加它们之间的空间以防止它们的合并，同时 也增加了他们的体积。