公开(公告)号：US10192792B2

公开(公告)日：2019-01-29

申请号：US15168336

申请日：2016-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Ryoung-han Kim

IPC: H01L27/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L23/535 ,  H01L27/02 ,  H01L29/66 ,  H01L27/118 ,  H01L21/8234 ,  H01L27/088

Abstract: A method of forming a logic cell utilizing a TS gate cross-couple construct and the resulting device are provided. Embodiments include forming active fins and dummy fins on a substrate, the dummy fins adjacent to each other and between the active fins; forming STI regions between and next to the active and dummy fins; forming gate structures in parallel across the active and dummy fins; forming a gate cut region by cutting the gate structures between the dummy fins; forming a TS layer between the gate structures, the TS layer crossing the gate cut region; and forming a contact connecting a gate structure and the TS layer on a first side of the gate cut region and forming a contact connecting a gate structure and the TS layer on a second side of the gate cut region, the TS layer and contacts cross coupling the gate structures.

公开(公告)号：US09490317B1

公开(公告)日：2016-11-08

申请号：US14712388

申请日：2015-05-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andre Labonte ,  Ryan Ryoung-han Kim

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/6656 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41783 ,  H01L29/66628 ,  H01L29/78

Abstract: There is set forth herein a gate contact structure for a gate. The gate contact structure can include a first contact layer and a second contact layer. In one embodiment, a gate contact layer can define a contact that provides a gate tie down. In one embodiment, a gate contact layer can have a minimum width larger than a gate length.

Abstract translation: 这里提出了用于门的栅极接触结构。 栅极接触结构可以包括第一接触层和第二接触层。 在一个实施例中，栅极接触层可以限定提供栅极接合的接触。 在一个实施例中，栅极接触层可以具有大于栅极长度的最小宽度。

公开(公告)号：US09484258B1

公开(公告)日：2016-11-01

申请号：US15071247

申请日：2016-03-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Ryoung-han Kim ,  Wenhui Wang ,  Lei Sun ,  Erik Verduijn ,  Yulu Chen

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/528

Abstract: A method for producing self-aligned vias (SAV) is provided. Embodiments include forming a ILOS layer over a dielectric layer; forming pairs of spacers over the ILOS layer, each pair of spacers having a first filler formed between adjacent spacers, and a second filler formed between each pair of spacers; forming and patterning a first OPL to expose one second filler, spacers on opposite sides of the one second filler, and a portion of the first filler adjacent each of the exposed spacers; removing the one second filler to form a SAV, and SAV etching into the ILOS layer; forming a second OPL over the first OPL and in the SAV to form a SAV plug; removing OPL layers and etching into the ILOS layer down to the dielectric layer; forming a third OPL layer in spaces between the TEOS layer; and removing the SAV plug.

Abstract translation: 提供了一种生产自对准通孔（SAV）的方法。 实施例包括在电介质层上形成ILOS层; 在ILOS层上形成隔离物对，每对隔离物具有形成在相邻间隔物之间​​的第一填料和在每对隔离物之间形成的第二填料; 形成和图案化第一OPL以暴露一个第二填料，一个第二填料的相对侧上的间隔物和与每个暴露间隔物相邻的第一填料的一部分; 去除一个第二填料以形成SAV，并且SAV蚀刻到ILOS层中; 在第一OPL和SAV上形成第二OPL以形成SAV插头; 去除OPL层并蚀刻到ILOS层中直到电介质层; 在TEOS层之间的空间中形成第三OPL层; 并卸下SAV插头。

公开(公告)号：US09478462B1

公开(公告)日：2016-10-25

申请号：US15071255

申请日：2016-03-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wenhui Wang ,  Ryan Ryoung-han Kim ,  Lei Sun ,  Erik Verduijn ,  Yulu Chen

IPC: H01L21/768 ,  H01L21/306 ,  H01L21/311 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/76808 ,  H01L21/76897 ,  H01L23/5226

Abstract: Methods of forming a SAV using a selective SAQP or SADP process are provided. Embodiments include providing on a TiN layer and dielectric layers alternating mandrels and non-mandrel fillers, spacers therebetween, and a metal cut plug through a mandrel or a non-mandrel filler; removing a non-mandrel filler through a SAV patterning stack having an opening over the non-mandrel filler and adjacent spacers, forming a trench; removing a mandrel through a second SAV patterning stack having an opening over the mandrel and adjacent spacers, forming a second trench; etching the trenches through the TiN and dielectric layers; forming plugs in the trenches; removing the mandrels and non-mandrel fillers, forming third trenches; etching the third trenches through the TiN layer; removing the metal cut plug and spacers and etching the third trenches into the dielectric layer; removing the plugs; and filling the trenches with metal.

Abstract translation: 提供了使用选择性SAQP或SADP方法形成SAV的方法。 实施例包括在TiN层和介电层上提供交替的心轴和非心轴填料，间隔件和通过心轴或非心轴填料的金属切割塞; 通过具有在非芯棒填料和相邻间隔物上的开口的SAV图案化叠层去除非芯棒填料，形成沟槽; 通过具有在所述心轴和相邻间隔物上的开口的第二SAV图案化叠层移除心轴，形成第二沟槽; 通过TiN和电介质层蚀刻沟槽; 在沟槽中形成插塞; 去除心轴和非心轴填料，形成第三沟槽; 蚀刻通过TiN层的第三沟槽; 去除金属切割塞子和间隔件并将第三沟槽蚀刻到介电层中; 取下插头; 并用金属填充沟槽。

公开(公告)号：US09406616B2

公开(公告)日：2016-08-02

申请号：US14561359

申请日：2014-12-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag Woo ,  Ryan Ryoung-han Kim

IPC: H01L27/12 ,  H01L21/84 ,  H01L27/092 ,  H01L23/535 ,  H01L27/11 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1211 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor device with uniform regular shaped gate contacts and the resulting device are disclosed. Embodiments include forming first and second gate electrodes adjacent one another on a substrate; forming at least one trench silicide (TS) on the substrate between the first and second gate electrodes; forming a gate contact on the first gate electrode, the gate contact having a regular shape; forming a source/drain contact on a trench silicide between the first and second gate electrodes, wherein an upper portion of the source/drain contact overlaps an upper portion of the gate contact.

Abstract translation: 公开了一种形成具有均匀的规则形状的栅极触点的半导体器件的方法以及所得到的器件。 实施例包括在基板上形成彼此相邻的第一和第二栅电极; 在所述第一和第二栅电极之间的所述衬底上形成至少一个沟槽硅化物（TS）; 在第一栅电极上形成栅极接触，栅接触具有规则形状; 在所述第一和第二栅电极之间的沟槽硅化物上形成源极/漏极接触，其中所述源极/漏极接触部的上部与所述栅极接触件的上部重叠。