公开(公告)号：US20140273365A1

公开(公告)日：2014-09-18

申请号：US13798503

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Shao Ming Koh

IPC: H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/823821 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/66795

Abstract: Various methods of forming conductive contacts to the source/drain regions of FinFET devices that involves forming a region comprised of a Schottkky barrier lowering material are disclosed. The method disclosed herein includes forming at least one fin for an N-type FinFET device (or a P-type FinFET device) in a semiconducting substrate, performing at least one process operation to form a region in the at least one fin that contains a Schottky barrier lowering material, depositing a layer of a valence band metal (for an N-type device) or a conduction band metal (for a P-type device) on the region and forming a metal silicide region on the fin, wherein the metal silicide is comprised of the valance band metal (for the N-type device) or a conduction band metal (for the P-type device).

Abstract translation: 公开了向包括形成由肖特基势垒降低材料构成的区域的FinFET器件的源极/漏极区域形成导电触点的各种方法。 本文公开的方法包括在半导体衬底中形成用于N型FinFET器件（或P型FinFET器件）的至少一个鳍片，执行至少一个工艺操作以在至少一个鳍片中形成包含 肖特基势垒降低材料，在该区域上沉积价带金属层（用于N型器件）或导带金属（用于P型器件），并在鳍片上形成金属硅化物区域，其中金属 硅化物由价带金属（用于N型器件）或导带金属（用于P型器件）组成。

公开(公告)号：US20160049490A1

公开(公告)日：2016-02-18

申请号：US14924151

申请日：2015-10-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Guillaume Bouche ,  Shao Ming Koh ,  Jeremy A. Wahl ,  Andy Wei

IPC: H01L29/45 ,  H01L27/092

CPC classification number: H01L29/45 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/41725

Abstract: Integrated circuits with dual silicide contacts are provided. In an embodiment, an integrated circuit includes a semiconductor substrate including a first area and a second area. The integrated circuit includes a first source/drain region in and/or overlying the first area of the semiconductor substrate and a second source/drain region in and/or overlying the second area of the semiconductor substrate. The integrated circuit further includes a first contact over the first source/drain region and comprising a first metal silicide. The integrated circuit also includes a second contact over the second source/drain region and comprising a second metal silicide different from the first metal silicide.

Abstract translation: 提供了具有双硅化物触点的集成电路。 在一个实施例中，集成电路包括包括第一区域和第二区域的半导体衬底。 集成电路包括位于半导体衬底的第一区域内和/或覆盖半导体衬底的第一区域的第一源极/漏极区域和位于半导体衬底的第二区域内和/或覆盖半导体衬底的第二区域中的第二源极/漏极区域。 集成电路还包括在第一源极/漏极区域上的第一接触并且包括第一金属硅化物。 集成电路还包括在第二源极/漏极区域上的第二接触并且包括不同于第一金属硅化物的第二金属硅化物。

公开(公告)号：US09117842B2

公开(公告)日：2015-08-25

申请号：US13798429

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Shao Ming Koh

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L29/66606 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545

Abstract: In one example, the method disclosed herein includes forming at least one fin for a FinFET device in a semiconducting substrate, performing at least one process operation to form a region in the at least one fin that contains a metal diffusion inhibiting material, depositing a layer of metal on the region in the at least one fin and forming a metal silicide region on the at least one fin.

Abstract translation: 在一个示例中，本文公开的方法包括在半导体衬底中形成用于FinFET器件的至少一个鳍，执行至少一个工艺操作以在至少一个鳍中形成包含金属扩散抑制材料的区域， 的至少一个翅片上的区域上的金属，并在所述至少一个翅片上形成金属硅化物区域。

公开(公告)号：US20150228755A1

公开(公告)日：2015-08-13

申请号：US14177800

申请日：2014-02-11

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Andy Wei ,  Jin Ping Liu ,  Shao Ming Koh ,  Amaury Gendron

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/8238

CPC classification number: H01L29/6681 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Integrated circuits with relaxed silicon and germanium fins and methods for fabricating such integrated circuits are provided. The method includes a forming a crystalline silicon and germanium composite layer overlying a crystalline silicon substrate, where a composite layer crystal lattice is relaxed. A fin is formed in the composite layer, and a gate is formed overlying the fin. A portion of the fin is removed on opposite sides of the gate to form a drain cavity and a source cavity, and a source and a drain are formed in the source cavity and drain cavity, respectively.

Abstract translation: 提供了具有松散硅和锗翅片的集成电路以及用于制造这种集成电路的方法。 该方法包括形成覆盖晶体硅衬底的晶体硅和锗复合层，其中复合层晶格被放宽。 在复合层中形成翅片，并且在翅片上形成栅极。 翅片的一部分在栅极的相对侧上被去除以形成漏腔和源腔，并且源极和漏极分别形成在源极腔和漏极腔中。

公开(公告)号：US20150214059A1

公开(公告)日：2015-07-30

申请号：US14166660

申请日：2014-01-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Guillaume Bouche ,  Shao Ming Koh ,  Jeremy A. Wahl ,  Andy C. Wei

IPC: H01L21/28 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/2807 ,  H01L21/28158 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795

Abstract: Integrated circuits having metal-insulator-semiconductor (MIS) contact structures and methods for fabricating integrated circuits having metal-insulator-semiconductor (MIS) contact structures are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure formed from semiconductor material overlying a semiconductor substrate. The method includes depositing a layer of high-k dielectric material over the fin structure. Further, the method includes forming a metal layer or layers over the layer of high-k dielectric material to provide the fin structure with a metal-insulator-semiconductor (MIS) contact structure.

Abstract translation: 提供了具有金属 - 绝缘体半导体（MIS）接触结构的集成电路以及用于制造具有金属 - 绝缘体 - 半导体（MIS））接触结构的集成电路的方法。 在一个实施例中，制造集成电路的方法包括提供由半导体材料覆盖在半导体衬底上形成的鳍结构。 该方法包括在鳍结构上沉积高k电介质材料层。 此外，该方法包括在高k电介质材料层上形成金属层，以使鳍结构具有金属 - 绝缘体半导体（MIS）接触结构。