公开(公告)号：US09673376B1

公开(公告)日：2017-06-06

申请号：US15014212

申请日：2016-02-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zoran Krivokapic ,  Bichoy Bahr

IPC: H01L29/84 ,  H01L41/107 ,  H01L41/29

CPC classification number: H01L41/107 ,  H01L29/78391 ,  H01L29/84 ,  H01L41/0474 ,  H01L41/29

Abstract: Methods to utilize piezoelectric materials as a gate dielectric in RBTs in an IC device to generate and sense higher frequency signals with high Qs and resulting devices are disclosed. Embodiments include forming, on an upper surface of a semiconductor layer, RBTs comprising even multiples of sensing RBTs and driving RBTs, each RBT including a piezoelectric gate dielectric layer, a gate, and a dielectric spacer on opposite sides of the piezoelectric gate dielectric layer and gate, wherein at least one pair of sensing RBTs is directly between two groups of driving RBTs; forming metal layers, separated by interlayer dielectric layers, above the RBTs; and forming vias through a dielectric layer above the RBTs connecting the RBTs to a metal layer.

公开(公告)号：US20190115437A1

公开(公告)日：2019-04-18

申请号：US16167081

申请日：2018-10-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Rohit Galatage ,  Steven Bentley ,  Puneet Harischandra Suvarna ,  Zoran Krivokapic

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/42324 ,  H01L21/28273 ,  H01L21/28291 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/788

Abstract: A semiconductor device includes a gate electrode structure that is positioned adjacent to a channel region of a transistor element. The gate electrode structure includes a floating gate electrode portion, a negative capacitor portion, and a ferroelectric material capacitively coupling the floating gate electrode portion to the negative capacitor portion. A first conductive material is positioned between the floating gate electrode portion and the ferroelectric material, wherein a first portion of the first conductive material is embedded in and laterally surrounded by the floating gate electrode portion, and a second conductive material is positioned between the first portion of the first conductive material and the ferroelectric material, wherein the second conductive material is embedded in and laterally surrounded by a second portion of the first conductive material.