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公开(公告)号：US12102020B2
公开(公告)日：2024-09-24
申请号：US17647006
申请日：2022-01-04
IPC分类号： H10N70/00
CPC分类号： H10N70/828 , H10N70/063 , H10N70/826 , H10N70/8418
摘要： A semiconductor memory device is provided. The memory device includes a first electrode, a resistive layer, and a second electrode. The resistive layer is arranged over the first electrode. The second electrode is arranged over the resistive layer. The second electrode includes a lower surface and an extension extending from under the lower surface. The extension is at least partially arranged within the resistive layer.
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公开(公告)号：US11855019B2
公开(公告)日：2023-12-26
申请号：US17173237
申请日：2021-02-11
CPC分类号： H01L24/05 , G01N27/225 , H01L24/03 , H01L24/06 , H01L2224/02206 , H01L2224/0382
摘要： The disclosed subject matter relates generally to methods of forming a semiconductor device, such as a moisture sensor. A plurality of electrodes and a bond pad are formed in a dielectric region. A passivation layer is formed on each electrode in the plurality of electrodes and the bond pad. A barrier layer is formed on the passivation layer. A plurality of trenches are formed to extend through the barrier layer and into the dielectric region. Formation of the trenches simultaneously exposes an upper surface of the bond pad. A moisture sensitive dielectric layer is formed on the barrier layer. Formation of the moisture sensitive dielectric layer also fills the trenches to form a plurality of projections, each projection being formed between two electrodes in the plurality of electrodes.
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公开(公告)号：US20230238342A1
公开(公告)日：2023-07-27
申请号：US17584507
申请日：2022-01-26
发明人： Hari Balan , Juan Boon Tan , Ramasamy Chockalingam , Wanbing Yi
IPC分类号： H01L23/00 , H01L25/065 , H01L23/528 , H01L25/00
CPC分类号： H01L24/08 , H01L25/0657 , H01L23/5286 , H01L24/80 , H01L25/50 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2924/1437
摘要： Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure includes a first field-effect transistor on a first substrate and a second field-effect transistor on a second substrate. The first field-effect transistor includes a first gate, and the second field-effect transistor includes a second gate. The structure further includes a first interconnect structure on the first substrate and a second interconnect structure on the second substrate. The first interconnect structure includes a first metal feature connected to the first gate, and the first metal feature has a first surface. The second interconnect structure includes a second metal feature connected to the second gate, and the second metal feature has a second surface that is connected to the first surface of the first metal feature.
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公开(公告)号：US11444045B2
公开(公告)日：2022-09-13
申请号：US16994644
申请日：2020-08-16
摘要： A semiconductor device is provided that includes a bond pad, an insulating layer, and a bonding structure. The bond pad is in a dielectric layer and the insulating layer is over the bond pad; the insulating layer having an opening over the bond pad formed therein. The bonding structure electrically couples the bond pad in the opening. The bonding structure has a height that at least extends to an upper surface of the insulating layer.
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公开(公告)号：US10892239B1
公开(公告)日：2021-01-12
申请号：US16508288
申请日：2019-07-10
摘要： The disclosed subject matter relates to a structure and method to improve bond pad reliability of semiconductor devices. According to an aspect of the present disclosure, a bond pad structure is provided that includes a dielectric layer and at least one bond pad in the dielectric layer, wherein the bond pad has a top surface. A passivation layer has an opening over the bond pad, wherein the opening has sidewalls. A low-k barrier layer is covering the sidewalls of the opening and the top surface of the bond pad. Protective structures are formed over the sidewalls of the opening.
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