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公开(公告)号：US12009326B2
公开(公告)日：2024-06-11
申请号：US17584507
申请日：2022-01-26
发明人： Hari Balan , Juan Boon Tan , Ramasamy Chockalingam , Wanbing Yi
IPC分类号： H01L23/00 , H01L23/528 , H01L25/00 , H01L25/065
CPC分类号： H01L24/08 , H01L23/5286 , H01L24/80 , H01L25/0657 , H01L25/50 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2924/1437
摘要： Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure includes a first field-effect transistor on a first substrate and a second field-effect transistor on a second substrate. The first field-effect transistor includes a first gate, and the second field-effect transistor includes a second gate. The structure further includes a first interconnect structure on the first substrate and a second interconnect structure on the second substrate. The first interconnect structure includes a first metal feature connected to the first gate, and the first metal feature has a first surface. The second interconnect structure includes a second metal feature connected to the second gate, and the second metal feature has a second surface that is connected to the first surface of the first metal feature.
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公开(公告)号：US12094763B2
公开(公告)日：2024-09-17
申请号：US17467477
申请日：2021-09-07
IPC分类号： H01L27/08 , H01L21/768 , H01L23/522 , H01L49/02
CPC分类号： H01L21/76811 , H01L21/76832 , H01L21/76843 , H01L23/5223 , H01L23/5226 , H01L27/0805 , H01L28/40
摘要： A device may include a first conductive element and an interlevel dielectric arranged over the first conductive element. The device may further include a dual damascene opening including a first end, a second end, and sidewalls extending between the first and second ends, the sidewalls extending through the interlevel dielectric. A metal-insulator-metal (MIM) stack may line the dual damascene opening. The MIM stack may include a first conductive liner lining the sidewalls and the second end of the dual damascene opening, an insulator layer lining the first conductive liner, and a second conductive liner lining the insulator layer. A first metal interconnect may be disposed in and filling the dual damascene opening lined with the MIM stack.
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公开(公告)号：US20230123402A1
公开(公告)日：2023-04-20
申请号：US17451172
申请日：2021-10-18
发明人： EeJan Khor , Ramasamy Chockalingam , Juan Boon Tan
IPC分类号： H01L49/02
摘要： A capacitor structure for an integrated circuit (IC) and a related method of forming are disclosed. The capacitor structure includes three electrodes. A planar bottom electrode has a first insulator layer thereover. A middle electrode includes a conductive layer over the first insulator layer and a plurality of spaced conductive pillars contacting the conductive layer. A second insulator layer extends over and between the plurality of spaced conductive pillars and contacts the conductive layer. An upper electrode extends over the second insulator layer, and hence, over and between the plurality of spaced conductive pillars. A length of the upper electrode can be controlled, in part, by the number and dimensions of the conductive pillars to increase capacitance capabilities per area.
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公开(公告)号：US11244915B2
公开(公告)日：2022-02-08
申请号：US16669531
申请日：2019-10-31
发明人： Ramasamy Chockalingam , Juan Boon Tan , Chee Kong Leong , Ranjan Rajoo , Xuesong Rao , Xiaodong Li
IPC分类号： H01L23/00
摘要： A semiconductor device is provided that includes a dielectric layer, a bond pad, a passivation layer and a planar barrier. The bond pad is positioned in the dielectric layer. The passivation layer is positioned over the dielectric layer and has an opening over the bond pad. The planar barrier is positioned on the bond pad.
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公开(公告)号：US10658316B2
公开(公告)日：2020-05-19
申请号：US16150242
申请日：2018-10-02
IPC分类号： H01L23/48 , H01L23/00 , H01L23/482 , H01L23/485 , H01L23/31 , H01L21/768 , H01L23/532 , H01L21/28 , H01L21/3065
摘要： According to an aspect of the present disclosure, a semiconductor device is provided that includes a substrate, at least one bond pad, a passivation layer and a NBLoK layer. The bond pad is formed over the substrate. The passivation layer is deposited over the substrate and has an opening defined by end portions of the passivation layer over the bond pad. The NBLoK layer is covering the end portions of the passivation layer.
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公开(公告)号：US10170437B1
公开(公告)日：2019-01-01
申请号：US15714503
申请日：2017-09-25
发明人： Ramasamy Chockalingam , Juan Boon Tan , Sung Mun Jung , Wenhu Liu , Ee Jan Khor
IPC分类号： H01L23/00 , H01L21/311 , H01L23/528 , H01L23/532 , H01L21/768 , H01L23/522
摘要： A method of forming a stop layer to prevent dummy vias from connecting to a metal layer and the resulting device are provided. Embodiments include forming a first metal layer in a first dielectric layer; forming a second dielectric layer over a first Nblok layer formed over the first dielectric and first metal layers; forming a third dielectric layer over the second dielectric layer and a second Nblok layer formed over a portion of the second dielectric layer; forming a via and a plurality of vias through the third and second dielectric layers down to the second and first Nblok layers, respectively; removing portions of the second and first Nblok layers through the via and the plurality of vias down to the second dielectric layer and the first metal layer, respectively; removing portions of the third dielectric layer through each via; and filling each via with a second metal layer.
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公开(公告)号：US12034039B2
公开(公告)日：2024-07-09
申请号：US17451172
申请日：2021-10-18
发明人： EeJan Khor , Ramasamy Chockalingam , Juan Boon Tan
IPC分类号： H01L49/02
CPC分类号： H01L28/92
摘要： A capacitor structure for an integrated circuit (IC) and a related method of forming are disclosed. The capacitor structure includes three electrodes. A planar bottom electrode has a first insulator layer thereover. A middle electrode includes a conductive layer over the first insulator layer and a plurality of spaced conductive pillars contacting the conductive layer. A second insulator layer extends over and between the plurality of spaced conductive pillars and contacts the conductive layer. An upper electrode extends over the second insulator layer, and hence, over and between the plurality of spaced conductive pillars. A length of the upper electrode can be controlled, in part, by the number and dimensions of the conductive pillars to increase capacitance capabilities per area.
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公开(公告)号：US20240038653A1
公开(公告)日：2024-02-01
申请号：US17816493
申请日：2022-08-01
IPC分类号： H01L23/522 , H01L49/02
CPC分类号： H01L23/5223 , H01L28/60
摘要： A structure for a capacitor is provided. The structure includes a first metal electrode, such as a copper electrode, having at least one dielectric region, such as a dielectric, therein. A first dielectric layer is on the first metal electrode, and a second metal electrode is on the first dielectric layer. At least one via is on the second metal electrode. Each via is over the at least one dielectric region in the first metal electrode.
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公开(公告)号：US11646279B2
公开(公告)日：2023-05-09
申请号：US17184659
申请日：2021-02-25
CPC分类号： H01L24/05 , H01L24/03 , H01L2224/0221 , H01L2224/0236 , H01L2224/02375 , H01L2224/02381 , H01L2224/04042 , H01L2224/05647
摘要： A semiconductor structure may be provided, including a conductive pad, a slot arranged through the conductive pad, a passivation layer arranged over the conductive pad and a plurality of electrical interconnects arranged under the conductive pad. The conductive pad may include an electrically conductive material and the slot may include an electrically insulating material. The passivation layer may include an opening that may expose a portion of the conductive pad and the slot may be arranged laterally between the exposed portion of the conductive pad and the plurality of electrical interconnects.
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公开(公告)号：US11217496B2
公开(公告)日：2022-01-04
申请号：US16404792
申请日：2019-05-07
发明人： Ramasamy Chockalingam , Juan Boon Tan , Wanbing Yi
摘要： A device and methods for forming the device is provided. The device includes a substrate and circuit elements thereon. The device further includes a metallization layer over the substrate. The metallization layer includes interconnects interconnecting the circuit elements. A test pad is disposed over an uppermost interconnect in the metallization layer. The test pad is coupled to one or more circuit elements via the interconnects. The test pad is configured for testing the one or more circuit elements. A crack stop protection seal surrounding the test pad is provided. The crack stop protection seal confines damage caused by probing at the test pad from propagating to an area beyond the crack stop protection seal.
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