公开(公告)号：US20240170560A1

公开(公告)日：2024-05-23

申请号：US17990898

申请日：2022-11-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Alexander Derrickson ,  Venkatesh Gopinath ,  John J. Pekarik ,  Hong Yu ,  Vibhor Jain ,  David Pritchard

IPC: H01L29/735 ,  H01L27/06 ,  H01L29/66 ,  H01L29/732

CPC classification number: H01L29/735 ,  H01L27/0623 ,  H01L29/66871 ,  H01L29/732

Abstract: Structures that include bipolar junction transistors and methods of forming such structures. The structure comprises a semiconductor layer, a substrate, and a dielectric layer disposed between the semiconductor layer and the substrate. The structure further comprises a first bipolar junction transistor including a first collector in the substrate, a first emitter, and a first base layer. The first base layer extends through the dielectric layer from the first emitter to the first collector. The structure further comprises a second bipolar junction transistor including a second collector in the substrate, a second emitter, and a second base layer. The second base layer extends through the dielectric layer from the second emitter to the second collector. The second base layer is connected to the first base layer by a section of the semiconductor layer to define a base line.

公开(公告)号：US20210242094A1

公开(公告)日：2021-08-05

申请号：US16776636

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Heng Yang ,  David Pritchard ,  Kai Sun ,  Hongru Ren ,  Neha Nayyar ,  Manjunatha Prabhu ,  Elizabeth Strehlow ,  Salvatore Cimino

IPC: H01L21/8238

Abstract: One illustrative vertical transistor device disclosed herein includes a channel region comprising at least one layer of a two-dimensional (2D) material, a bottom source/drain region, a top source/drain region and a gate structure positioned all around at least the at least one layer of a two-dimensional (2D) material.