RESISTIVE MEMORY ELEMENT ARRAYS WITH SHARED ELECTRODE STRIPS

    公开(公告)号:US20240023345A1

    公开(公告)日:2024-01-18

    申请号:US17866756

    申请日:2022-07-18

    Abstract: Structures that include resistive memory elements and methods of forming a structure that includes resistive memory elements. The structure comprises a first plurality of resistive memory elements including a first plurality of bottom electrodes, a first top electrode, and a first switching layer between the first top electrode and the first plurality of bottom electrodes. The structure further comprises a second plurality of resistive memory elements including a second plurality of bottom electrodes, a second top electrode, and a second switching layer between the second top electrode and the second plurality of bottom electrodes. The first top electrode is shared by the first plurality of resistive memory elements, and the second top electrode is shared by the second plurality of resistive memory elements.

    BIPOLAR JUNCTION TRANSISTOR ARRAYS
    2.
    发明公开

    公开(公告)号:US20240170560A1

    公开(公告)日:2024-05-23

    申请号:US17990898

    申请日:2022-11-21

    CPC classification number: H01L29/735 H01L27/0623 H01L29/66871 H01L29/732

    Abstract: Structures that include bipolar junction transistors and methods of forming such structures. The structure comprises a semiconductor layer, a substrate, and a dielectric layer disposed between the semiconductor layer and the substrate. The structure further comprises a first bipolar junction transistor including a first collector in the substrate, a first emitter, and a first base layer. The first base layer extends through the dielectric layer from the first emitter to the first collector. The structure further comprises a second bipolar junction transistor including a second collector in the substrate, a second emitter, and a second base layer. The second base layer extends through the dielectric layer from the second emitter to the second collector. The second base layer is connected to the first base layer by a section of the semiconductor layer to define a base line.

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