公开(公告)号：US11239087B2

公开(公告)日：2022-02-01

申请号：US16662091

申请日：2019-10-24

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Heng Yang ,  David C. Pritchard ,  George J. Kluth ,  Anurag Mittal ,  Hongru Ren ,  Manjunatha G. Prabhu ,  Kai Sun ,  Neha Nayyar ,  Lixia Lei

IPC: H01L27/12 ,  H01L21/308 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L21/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.

公开(公告)号：US11177182B2

公开(公告)日：2021-11-16

申请号：US16776636

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Heng Yang ,  David Pritchard ,  Kai Sun ,  Hongru Ren ,  Neha Nayyar ,  Manjunatha Prabhu ,  Elizabeth Strehlow ,  Salvatore Cimino

IPC: H01L29/66 ,  H01L21/8238

Abstract: One illustrative vertical transistor device disclosed herein includes a channel region comprising at least one layer of a two-dimensional (2D) material, a bottom source/drain region, a top source/drain region and a gate structure positioned all around at least the at least one layer of a two-dimensional (2D) material.

公开(公告)号：US20210242094A1

公开(公告)日：2021-08-05

申请号：US16776636

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Heng Yang ,  David Pritchard ,  Kai Sun ,  Hongru Ren ,  Neha Nayyar ,  Manjunatha Prabhu ,  Elizabeth Strehlow ,  Salvatore Cimino

IPC: H01L21/8238

Abstract: One illustrative vertical transistor device disclosed herein includes a channel region comprising at least one layer of a two-dimensional (2D) material, a bottom source/drain region, a top source/drain region and a gate structure positioned all around at least the at least one layer of a two-dimensional (2D) material.

公开(公告)号：US11094791B1

公开(公告)日：2021-08-17

申请号：US16776711

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Heng Yang ,  David Pritchard ,  Kai Sun ,  Hongru Ren ,  Neha Nayyar ,  Manjunatha Prabhu ,  Elizabeth Strehlow ,  Salvatore Cimino

IPC: H01L29/47 ,  H01L29/417 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08

Abstract: One illustrative device disclosed herein includes a bottom source/drain region and a top source/drain region positioned vertically above at least a portion of the bottom source/drain region, wherein each of the bottom source/drain region and the top source/drain region comprise at least one layer of a two-dimensional (2D) material. The device also includes a substantially vertically oriented semiconductor structure positioned vertically between the bottom source/drain region and the top source/drain region and a gate structure positioned all around an outer perimeter of the substantially vertically oriented semiconductor structure for at least a portion of the vertical height of the substantially vertically oriented semiconductor structure.

公开(公告)号：US11276651B2

公开(公告)日：2022-03-15

申请号：US16876532

申请日：2020-05-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anton Tokranov ,  Kai Sun ,  Elizabeth Strehlow ,  James Mazza ,  David Pritchard ,  Heng Yang ,  Mohamed Rabie

IPC: H01L23/00 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

Abstract: An illustrative device disclosed herein includes a semiconductor substrate and a FinFET transistor device positioned above the semiconductor substrate, wherein the FinFET transistor device has a single active fin structure. The device also includes an electrically inactive dummy fin structure positioned adjacent the single active fin structure, wherein the electrically inactive dummy fin structure is electrically inactive with respect to electrical operation of the FinFET transistor having the single active fin.

公开(公告)号：US20210358865A1

公开(公告)日：2021-11-18

申请号：US16876532

申请日：2020-05-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anton Tokranov ,  Kai Sun ,  Elizabeth Strehlow ,  James Mazza ,  David Pritchard ,  Heng Yang ,  Mohamed Rabie

IPC: H01L23/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

Abstract: An illustrative device disclosed herein includes a semiconductor substrate and a FinFET transistor device positioned above the semiconductor substrate, wherein the FinFET transistor device has a single active fin structure. The device also includes an electrically inactive dummy fin structure positioned adjacent the single active fin structure, wherein the electrically inactive dummy fin structure is electrically inactive with respect to electrical operation of the FinFET transistor having the single active fin.

公开(公告)号：US20210242316A1

公开(公告)日：2021-08-05

申请号：US16776711

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Heng Yang ,  David Pritchard ,  Kai Sun ,  Hongru Ren ,  Neha Nayyar ,  Manjunatha Prabhu ,  Elizabeth Strehlow ,  Salvatore Cimino

IPC: H01L29/417 ,  H01L29/16 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66

Abstract: One illustrative device disclosed herein includes a bottom source/drain region and a top source/drain region positioned vertically above at least a portion of the bottom source/drain region, wherein each of the bottom source/drain region and the top source/drain region comprise at least one layer of a two-dimensional (2D) material. The device also includes a substantially vertically oriented semiconductor structure positioned vertically between the bottom source/drain region and the top source/drain region and a gate structure positioned all around an outer perimeter of the substantially vertically oriented semiconductor structure for at least a portion of the vertical height of the substantially vertically oriented semiconductor structure.