公开(公告)号：US20240345983A1

公开(公告)日：2024-10-17

申请号：US18757574

申请日：2024-06-28

申请人： Sridhar Muthrasanallur ,  Swadesh Choudhary ,  Debendra Das Sharma

发明人： Sridhar Muthrasanallur ,  Swadesh Choudhary ,  Debendra Das Sharma

IPC分类号： G06F13/42 ,  G06F13/38

CPC分类号： G06F13/4221 ,  G06F13/382 ,  G06F2213/0026

摘要： For example, an Integrated Circuit, e.g., a chiplet, may include Physical layer (PHY) circuitry to communicate with another IC, e.g., chiplet, over a Universal Chiplet Interconnect Express (UCIe) link. For example, the IC may include a System on Chip (SoC) bridge, which may be configured to transport a plurality of Management Transport Packets (MTPs) over a plurality of connection links of the UCIe link. For example, the SoC bridge may be configured to transport the plurality of MTPs according to a predefined interleaving scheme. For example, the predefined interleaving scheme may define a predefined order of assignment of a plurality of credit-path MTPs to a plurality of Receive (R×) Queue Identifiers (R×Q-IDs) corresponding to the plurality of connection links.

公开(公告)号：US20220012140A1

公开(公告)日：2022-01-13

申请号：US17485180

申请日：2021-09-24

申请人： Debendra Das Sharma ,  Michelle C. Jen ,  Swadesh Choudhary ,  Raghucharan Boddupalli

发明人： Debendra Das Sharma ,  Michelle C. Jen ,  Swadesh Choudhary ,  Raghucharan Boddupalli

IPC分类号： G06F11/14 ,  G06F13/42

摘要： A device includes a port with a replay buffer and protocol logic to receive a flit in a sequence of flits to be sent on a point-to-point link and determine an error in the flit. Based on the error, a copy of the flit is stored in a first position within the replay buffer as well as a copy of a next flit received in the sequence of flits, which is stored in a second position within the replay buffer. The copies of the flits are then written to a register for access by software.

公开(公告)号：US20200304150A1

公开(公告)日：2020-09-24

申请号：US16900637

申请日：2020-06-12

申请人： Debendra Das Sharma ,  Swadesh Choudhary

发明人： Debendra Das Sharma ,  Swadesh Choudhary

IPC分类号： H03M13/15 ,  G06F13/42

摘要： Embodiments herein describe a FEC codec for generating a check byte for a message. The FEC codec includes a port encoder having a storage unit, a Galois field multiplier, and a sum unit. The storage unit stores a first staged result, which is accumulated based on previous sets of input bytes of the message for all clock cycles from a first clock cycle to a clock cycle immediately prior to the current clock cycle. The Galois field multiplier performs a Galois field multiplication of the first staged result and a power of the alpha to generate a Galois field product. The sum unit performs a Galois field addition on an internal input based on a consolidated byte for the current clock cycle and the Galois field product to generate a second staged result for subsequent use to generate the check byte. Other embodiments may be described and/or claimed.

公开(公告)号：US20190236038A1

公开(公告)日：2019-08-01

申请号：US16227364

申请日：2018-12-20

申请人： Swadesh Choudhary ,  Bahaa Fahim ,  Doddaballapur Jayashimha ,  Jeffrey Chamberlain ,  Yen-Cheng Liu

发明人： Swadesh Choudhary ,  Bahaa Fahim ,  Doddaballapur Jayashimha ,  Jeffrey Chamberlain ,  Yen-Cheng Liu

IPC分类号： G06F13/20 ,  G06F13/40

CPC分类号： G06F13/20 ,  G06F13/4027

摘要： Buffered interconnects for highly scalable on-die fabric and associated methods and apparatus. A plurality of nodes on a die are interconnected via an on-die fabric. The nodes and fabric are configured to implement forwarding of credited messages from source nodes to destination nodes using forwarding paths partitioned into a plurality of segments, wherein separate credit loops are implemented for each segment. Under one fabric configuration implementing an approach called multi-level crediting, the nodes are configured in a two-dimensional grid and messages are forwarded using vertical and horizontal segments, wherein a first segment is between a source node and a turn node in the same row or column and the second segment is between the turn node and a destination node. Under another approach called buffered mesh, buffering and credit management facilities are provided at each node and adjacent nodes are configured to implement credit loops for forwarding messages between the nodes. The fabrics may comprise various topologies, including 2D mesh topologies and ring interconnect structures. Moreover, multi-level crediting and buffered mesh may be used for forwarding messages across dies.

公开(公告)号：US20200327084A1

公开(公告)日：2020-10-15

申请号：US16914327

申请日：2020-06-27

申请人： Swadesh Choudhary ,  Robert G. Blankenship ,  Siva Prasad Gadey ,  Sailesh Kumar ,  Vinit Mathew Abraham ,  Yen-Cheng Liu

发明人： Swadesh Choudhary ,  Robert G. Blankenship ,  Siva Prasad Gadey ,  Sailesh Kumar ,  Vinit Mathew Abraham ,  Yen-Cheng Liu

IPC分类号： G06F13/40

摘要： An interface for coupling an agent to a fabric supports a set of coherent interconnect protocols and includes a global channel to communicate control signals to support the interface, a request channel to communicate messages associated with requests to other agents on the fabric, a response channel to communicate responses to other agents on the fabric, and a data channel to couple to communicate messages associated with data transfers to other agents on the fabric, where the data transfers include payload data.

公开(公告)号：US20230342323A1

公开(公告)日：2023-10-26

申请号：US18345208

申请日：2023-06-30

申请人： Mohannad Fahim Ali ,  Swadesh Choudhary ,  Joji Philip ,  David J. Harriman

发明人： Mohannad Fahim Ali ,  Swadesh Choudhary ,  Joji Philip ,  David J. Harriman

IPC分类号： G06F13/42

CPC分类号： G06F13/4221 ,  G06F2213/0026

摘要： An interface for coupling an agent to a fabric supports a load/store interconnect protocol, where the I/O interconnect protocol includes a flit mode and a non-flit mode. A set of flit mode header formats are used when in the flit mode and a set of non-flit mode header formats are used when in the non-flit mode, the set of non-flit mode header formats including one or more non-flit mode fields. Interface logic determines that a link is trained to the non-flit mode and generates a header according to the set of flit mode header formats, where the header includes a field to indicate that a corresponding packet originated as a non-flit mode packet. One or more fields of the set of flit mode header formats are repurposed in the header to carry the one or more non-flit mode fields before sending the modified header over the interface.

公开(公告)号：US20230237168A1

公开(公告)日：2023-07-27

申请号：US18193231

申请日：2023-03-30

申请人： Swadesh Choudhary ,  Robert Blankenship ,  Mohannad Fahim Ali ,  Raghunandan Makaram

发明人： Swadesh Choudhary ,  Robert Blankenship ,  Mohannad Fahim Ali ,  Raghunandan Makaram

IPC分类号： G06F21/60 ,  G06F21/85

CPC分类号： G06F21/602 ,  G06F21/85

摘要： Embodiments herein relate to an electronic device with an interface an interface to communicatively couple with a second electronic device via a communication link, and a link controller. The link controller may be configured to identify, from the second electronic device over the communication link, a flit related to a request from the second electronic device to access a resource of the first electronic device, wherein the flit is an element of a message authentication code (MAC) epoch; generate, based on the flit, a cache/mem interface message related to the request, wherein the cache/mem interface message includes an indication of the MAC epoch; and transmit, to a device fabric of the first electronic device, the cache/mem interface message prior to receipt of a MAC related to the MAC epoch. Other embodiments may be described and/or claimed.

公开(公告)号：US20190227979A1

公开(公告)日：2019-07-25

申请号：US16369220

申请日：2019-03-29

申请人： Brinda Ganesh ,  Yen-Cheng Liu ,  Swadesh Choudhary ,  Tejpal Singh ,  Pradeep Prabhakaran ,  Monam Agarwal

发明人： Brinda Ganesh ,  Yen-Cheng Liu ,  Swadesh Choudhary ,  Tejpal Singh ,  Pradeep Prabhakaran ,  Monam Agarwal

IPC分类号： G06F15/173 ,  G06F13/40 ,  H01L21/768 ,  H01L25/065

摘要： In one embodiment, a system on chip includes: a plurality of intellectual property (IP) agents formed on a semiconductor die; a mesh interconnect formed on the semiconductor die to couple the plurality of IP agents, and a plurality of mesh stops each to couple one or more of the plurality of IP agents to the mesh interconnect. The mesh interconnect may be formed of a plurality of rows each having one of a plurality of horizontal interconnects and a plurality of columns each having one of a plurality of vertical interconnects;, where at least one of the plurality of rows includes an asymmetrical number of mesh stops. Other embodiments are described and claimed.