公开(公告)号：US20220012140A1

公开(公告)日：2022-01-13

申请号：US17485180

申请日：2021-09-24

申请人： Debendra Das Sharma ,  Michelle C. Jen ,  Swadesh Choudhary ,  Raghucharan Boddupalli

发明人： Debendra Das Sharma ,  Michelle C. Jen ,  Swadesh Choudhary ,  Raghucharan Boddupalli

IPC分类号： G06F11/14 ,  G06F13/42

摘要： A device includes a port with a replay buffer and protocol logic to receive a flit in a sequence of flits to be sent on a point-to-point link and determine an error in the flit. Based on the error, a copy of the flit is stored in a first position within the replay buffer as well as a copy of a next flit received in the sequence of flits, which is stored in a second position within the replay buffer. The copies of the flits are then written to a register for access by software.

公开(公告)号：US20220261308A1

公开(公告)日：2022-08-18

申请号：US17733627

申请日：2022-04-29

申请人： Narasimha Lanka ,  Debendra Das Sharma ,  Lakshmipriya Seshan ,  Swadesh Choudhary ,  Zuoguo Wu ,  Gerald Pasdast

发明人： Narasimha Lanka ,  Debendra Das Sharma ,  Lakshmipriya Seshan ,  Swadesh Choudhary ,  Zuoguo Wu ,  Gerald Pasdast

IPC分类号： G06F11/10 ,  G06F11/07 ,  G06F13/40

摘要： Embodiments herein relate to a die of a multi-die package, wherein the die is coupled with another die via a die-to-die (D2D) interconnect link. The die may transmit a data signal to the other die via a data lane of the D2D interconnect link. The die may further transmit, concurrently with the data signal, a valid signal to the other die via a valid lane of the D2D interconnect link. The valid signal may change logical state at least once during the transmission of the data signal. Other embodiments may be described and claimed.

公开(公告)号：US20210232520A1

公开(公告)日：2021-07-29

申请号：US17231152

申请日：2021-04-15

申请人： Swadesh Choudhary ,  Mahesh Wagh ,  Debendra Das Sharma

发明人： Swadesh Choudhary ,  Mahesh Wagh ,  Debendra Das Sharma

IPC分类号： G06F13/38 ,  G06F13/40 ,  G06F11/10

摘要： In one embodiment, an apparatus includes: a first link layer circuit to perform link layer functionality for a first communication protocol; and a logical physical (logPHY) circuit coupled to the first link layer circuit via a logical PHY interface (LPIF) link, the logPHY circuit to communicate with the first link layer circuit in a flit mode in which the first information is communicated in a fixed width size and to communicate with another link layer circuit in a non-flit mode. Other embodiments are described and claimed.

公开(公告)号：US20220334995A1

公开(公告)日：2022-10-20

申请号：US17855687

申请日：2022-06-30

申请人： Debendra Das Sharma ,  Mahesh S. Natu ,  Sridhar Muthrasanallur ,  Swadesh Choudhary ,  Narasimha Lanka ,  Lakshmipriya Seshan

发明人： Debendra Das Sharma ,  Mahesh S. Natu ,  Sridhar Muthrasanallur ,  Swadesh Choudhary ,  Narasimha Lanka ,  Lakshmipriya Seshan

IPC分类号： G06F13/40 ,  G06F13/42

摘要： A port is to couple to another die over a die-to-die (D2D) link and includes a die-tio-die (D2D) adapter to determine, from a set of registers, a set of capabilities of the D2D adapter to advertise in a negotiation with a link partner D2D adapter, where the D2D adapter is on a die and the link partner D2D adapter is located on a remote link partner die. A first capabilities advertisement message is sent to the link partner D2D adapter to advertise the set of capabilities to the link partner D2D adapter. A second capabilities advertisement message is received from the link partner D2D adapter, wherein the second capabilities advertisement message identifies a set of capabilities of the link partner D2D adapter. A final configuration of a D2D link is determined to couple the die to the link partner die.

公开(公告)号：US20240345983A1

公开(公告)日：2024-10-17

申请号：US18757574

申请日：2024-06-28

申请人： Sridhar Muthrasanallur ,  Swadesh Choudhary ,  Debendra Das Sharma

发明人： Sridhar Muthrasanallur ,  Swadesh Choudhary ,  Debendra Das Sharma

IPC分类号： G06F13/42 ,  G06F13/38

CPC分类号： G06F13/4221 ,  G06F13/382 ,  G06F2213/0026

摘要： For example, an Integrated Circuit, e.g., a chiplet, may include Physical layer (PHY) circuitry to communicate with another IC, e.g., chiplet, over a Universal Chiplet Interconnect Express (UCIe) link. For example, the IC may include a System on Chip (SoC) bridge, which may be configured to transport a plurality of Management Transport Packets (MTPs) over a plurality of connection links of the UCIe link. For example, the SoC bridge may be configured to transport the plurality of MTPs according to a predefined interleaving scheme. For example, the predefined interleaving scheme may define a predefined order of assignment of a plurality of credit-path MTPs to a plurality of Receive (R×) Queue Identifiers (R×Q-IDs) corresponding to the plurality of connection links.

公开(公告)号：US20220342841A1

公开(公告)日：2022-10-27

申请号：US17856050

申请日：2022-07-01

申请人： Swadesh Choudhary ,  Debendra Das Sharma ,  Narasimha Lanka ,  Lakshmipriya Seshan ,  Gerald Pasdast ,  Zuoguo Wu

发明人： Swadesh Choudhary ,  Debendra Das Sharma ,  Narasimha Lanka ,  Lakshmipriya Seshan ,  Gerald Pasdast ,  Zuoguo Wu

IPC分类号： G06F13/42 ,  G06F11/10

摘要： A die-to-die (D2D) adapter couples to a protocol layer block using a first interface to couple to a protocol layer block and couples to a physical layer (PHY) block using a second interface. The D2D adapter is to determine parameters of a D2D link to couple a first die to a second die and select, based on the parameters, a particular one of a plurality of different data formats for use on the D2D link. Protocol layer data is received at the D2D adapter over the first interface from the protocol layer block. The D2D adapter passes the protocol layer data over the second interface to the PHY block based on the particular data format.

公开(公告)号：US20220271912A1

公开(公告)日：2022-08-25

申请号：US17743085

申请日：2022-05-12

申请人： Gerald Pasdast ,  Peipei Wang ,  Lakshmipriya Seshan ,  Juan Zeng ,  Zuoguo Wu ,  Zhiguo Qian ,  Narasimha Lanka ,  Debendra Das Sharma ,  Swadesh Choudhary

发明人： Gerald Pasdast ,  Peipei Wang ,  Lakshmipriya Seshan ,  Juan Zeng ,  Zuoguo Wu ,  Zhiguo Qian ,  Narasimha Lanka ,  Debendra Das Sharma ,  Swadesh Choudhary

IPC分类号： H04L7/00

摘要： Embodiments herein may relate to a die for use in a multi-die package. The die may include clock circuitry that is able to identify a phase of a data signal to be transmitted and a phase of a clock signal to be transmitted on a die-to-die (D2D) link. The clock circuitry may further be configured adjust the phase of the clock signal such that the phase of the clock signal is approximately 90 degrees from the phase of the data signal such that the clock signal and the data signal are received by a receiver die of the D2D link with a 90 degree phase difference. Other embodiments may be described and claimed.

公开(公告)号：US20220334932A1

公开(公告)日：2022-10-20

申请号：US17855720

申请日：2022-06-30

申请人： Debendra Das Sharma ,  Swadesh Choudhary ,  Sridhar Muthrasanallur ,  Narasimha Lanka ,  Zuoguo Wu ,  Gerald Pasdast ,  Lakshmipriya Seshan

发明人： Debendra Das Sharma ,  Swadesh Choudhary ,  Sridhar Muthrasanallur ,  Narasimha Lanka ,  Zuoguo Wu ,  Gerald Pasdast ,  Lakshmipriya Seshan

IPC分类号： G06F11/20 ,  G06F13/42 ,  G06F13/40 ,  G06F13/16 ,  G06F11/08

摘要： A retimer includes a first port to couple to a die over a first interconnect, where the first interconnect includes a defined set of lanes and utilizes a first communication technology, and the die is located on a first package with the retimer. The retimer further includes a second port to couple to another retimer over a second interconnect, where the second interconnect utilizes a different second communication technology, and the second retimer is located on a different, second package to facilitate a longer reach communication channel.

公开(公告)号：US20220262756A1

公开(公告)日：2022-08-18

申请号：US17733545

申请日：2022-04-29

申请人： Narasimha Lanka ,  Debendra Das Sharma ,  Lakshmipriya Seshan ,  Gerald Pasdast ,  Zuoguo Wu ,  Swadesh Choudhary

发明人： Narasimha Lanka ,  Debendra Das Sharma ,  Lakshmipriya Seshan ,  Gerald Pasdast ,  Zuoguo Wu ,  Swadesh Choudhary

IPC分类号： H01L23/00 ,  H01L25/10 ,  G06F1/04 ,  H01L23/12 ,  H01L23/538

摘要： Embodiments herein relate to action that are to be taken on various lanes of a die-to-die (D2D) interconnect in the event of clock-gating. Specifically, based on identification that a clock-gating event is to occur, physical layer (PHY) logic may direct PHY electrical circuitry to set the state of various of the lanes. In some embodiments, different actions may be taken based on whether the D2D interconnect is terminated or unterminated. Other embodiments may be described and claimed.

公开(公告)号：US20220237138A1

公开(公告)日：2022-07-28

申请号：US17708386

申请日：2022-03-30

申请人： Narasimha Lanka ,  Lakshmipriya Seshan ,  Swadesh Choudhary ,  Debendra Das Sharma ,  Zuoguo Wu ,  Gerald Pasdast

发明人： Narasimha Lanka ,  Lakshmipriya Seshan ,  Swadesh Choudhary ,  Debendra Das Sharma ,  Zuoguo Wu ,  Gerald Pasdast

IPC分类号： G06F13/40 ,  G06F1/10

摘要： In one embodiment, an apparatus includes: a die-to-die adapter to communicate with a protocol layer and physical layer circuitry, and the physical layer circuitry coupled to the die-to-die adapter, where the physical layer circuitry is to receive and output first information to a second die via an interconnect. The physical layer circuitry, after a reset flow for the first die, is to: perform a sideband initialization of a sideband interface of the interconnect to detect that the second die has completed a reset flow for the second die; and after the sideband initialization, perform a mainband initialization of a mainband interface of the interconnect at a lowest speed, and thereafter perform a mainband training of the mainband interface at a negotiated data rate. Other embodiments are described and claimed.