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    Inclusive/Non Inclusive Tracking of Local Cache Lines To Avoid Near Memory Reads On Cache Line Memory Writes Into A Two Level System Memory
    5.
    发明申请
    Inclusive/Non Inclusive Tracking of Local Cache Lines To Avoid Near Memory Reads On Cache Line Memory Writes Into A Two Level System Memory 有权
    包含/非包含性跟踪本地缓存线以避免缓存行内存上的近内存读取写入两级系统内存

    公开(公告)号：US20150186275A1

    公开(公告)日：2015-07-02

    申请号：US14142045

    申请日：2013-12-27

    申请人： Adrian C. Moga ,  Vedaraman Geetha ,  Bahaa Fahim ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Jeffrey D. Chamberlain ,  Stephen R. Van Doren

    发明人： Adrian C. Moga ,  Vedaraman Geetha ,  Bahaa Fahim ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Jeffrey D. Chamberlain ,  Stephen R. Van Doren

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0811 ,  G06F12/0888

    摘要： A processor is described that includes one or more processing cores. The processing core includes a memory controller to interface with a system memory having a near memory and a far memory. The processing core includes a plurality of caching levels above the memory controller. The processor includes logic circuitry to track state information of a cache line that is cached in one of the caching levels. The state information including a selected one of an inclusive state and a non inclusive state. The inclusive state indicates that a copy or version of the cache line exists in near memory. The non inclusive states indicates that a copy or version of the cache line does not exist in the near memory. The logic circuitry is to cause the memory controller to handle a write request that requests a direct write into the near memory without a read of the near memory beforehand if a system memory write request generated within the processor targets the cache line when the cache line is in the inclusive state.

    摘要翻译： 描述了包括一个或多个处理核心的处理器。 处理核心包括与具有近存储器和远存储器的系统存储器接口的存储器控​​制器。 处理核心包括存储器控制器上方的多个缓存级别。 处理器包括用于跟踪高速缓存行的状态信息的逻辑电路，该高速缓存行被缓存在缓存级之一中。 所述状态信息包括包含状态和不包含状态中的所选择的状态。 包含状态表示在内存中存在高速缓存行的副本或版本。 不包含状态表示高速缓存行的副本或版本不存在于近端存储器中。 逻辑电路是使存储器控制器处理写入请求，如果在处理器内部产生的系统存储器写入请求在高速缓存线为 在包容性状态。

    Pass through debug port on a high speed asynchronous link
    8.
    发明授权
    Pass through debug port on a high speed asynchronous link 有权
    通过高速异步链路上的调试端口

    公开(公告)号：US07328375B2

    公开(公告)日：2008-02-05

    申请号：US10749660

    申请日：2003-12-30

    申请人： Ashish Gupta ,  Bahaa Fahim ,  Kent Dickey ,  Jonathan Jasper

    发明人： Ashish Gupta ,  Bahaa Fahim ,  Kent Dickey ,  Jonathan Jasper

    IPC分类号： G06F11/00

    CPC分类号： H04L7/046

    摘要： An example computer system includes a first bridge device that includes an interface controller. The interface controller combines debug information generated within the bridge device with a training pattern. The first bridge device is coupled to a second bridge device via a high-speed asynchronous interconnect. The first bridge device converts the debug information and training pattern into a packet to be transmitted over the interconnect to the second bridge device. The training pattern serves to allow the second bridge device to maintain bit and symbol synchronization during the transfer; of the debug information.

    摘要翻译： 示例性计算机系统包括包括接口控制器的第一桥接设备。 接口控制器将桥接设备内生成的调试信息与训练模式相结合。 第一桥接器件经由高速异步互连耦合到第二桥接器件。 第一桥接器件将调试信息和训练模式转换成要通过互连发送到第二桥接器件的分组。 训练模式用于允许第二桥接设备在传送期间维持比特和符号同步; 的调试信息。

    Pass through debug port on a high speed asynchronous link
    9.
    发明申请
    Pass through debug port on a high speed asynchronous link 有权
    通过高速异步链路上的调试端口

    公开(公告)号：US20050149705A1

    公开(公告)日：2005-07-07

    申请号：US10749660

    申请日：2003-12-30

    申请人： Ashish Gupta ,  Bahaa Fahim ,  Kent Dickey ,  Jonathan Jasper

    发明人： Ashish Gupta ,  Bahaa Fahim ,  Kent Dickey ,  Jonathan Jasper

    IPC分类号： G06F7/38 ,  G06F13/00 ,  H04L7/04

    CPC分类号： H04L7/046

    摘要： An example computer system includes a first bridge device that includes an interface controller. The interface controller combines debug information generated within the bridge device with a training pattern. The first bridge device is coupled to a second bridge device via a high-speed asynchronous interconnect. The first bridge device converts the debug information and training pattern into a packet to be transmitted over the interconnect to the second bridge device. The training pattern serves to allow the second bridge device to maintain bit and symbol synchronization during the transfer; of the debug information.

    摘要翻译： 示例性计算机系统包括包括接口控制器的第一桥接设备。 接口控制器将桥接设备内生成的调试信息与训练模式相结合。 第一桥接器件经由高速异步互连耦合到第二桥接器件。 第一桥接器件将调试信息和训练模式转换成要通过互连发送到第二桥接器件的分组。 训练模式用于允许第二桥接设备在传送期间维持比特和符号同步; 的调试信息。

    BUFFERED INTERCONNECT FOR HIGHLY SCALABLE ON-DIE FABRIC
    10.
    发明申请
    BUFFERED INTERCONNECT FOR HIGHLY SCALABLE ON-DIE FABRIC 审中-公开

    公开(公告)号：US20190236038A1

    公开(公告)日：2019-08-01

    申请号：US16227364

    申请日：2018-12-20

    申请人： Swadesh Choudhary ,  Bahaa Fahim ,  Doddaballapur Jayashimha ,  Jeffrey Chamberlain ,  Yen-Cheng Liu

    发明人： Swadesh Choudhary ,  Bahaa Fahim ,  Doddaballapur Jayashimha ,  Jeffrey Chamberlain ,  Yen-Cheng Liu

    IPC分类号： G06F13/20 ,  G06F13/40

    CPC分类号： G06F13/20 ,  G06F13/4027

    摘要： Buffered interconnects for highly scalable on-die fabric and associated methods and apparatus. A plurality of nodes on a die are interconnected via an on-die fabric. The nodes and fabric are configured to implement forwarding of credited messages from source nodes to destination nodes using forwarding paths partitioned into a plurality of segments, wherein separate credit loops are implemented for each segment. Under one fabric configuration implementing an approach called multi-level crediting, the nodes are configured in a two-dimensional grid and messages are forwarded using vertical and horizontal segments, wherein a first segment is between a source node and a turn node in the same row or column and the second segment is between the turn node and a destination node. Under another approach called buffered mesh, buffering and credit management facilities are provided at each node and adjacent nodes are configured to implement credit loops for forwarding messages between the nodes. The fabrics may comprise various topologies, including 2D mesh topologies and ring interconnect structures. Moreover, multi-level crediting and buffered mesh may be used for forwarding messages across dies.