公开(公告)号：US07688651B2

公开(公告)日：2010-03-30

申请号：US11756750

申请日：2007-06-01

Applicant: Chi-wook Kim ,  Tai-young Ko

Inventor： Chi-wook Kim ,  Tai-young Ko

IPC: G11C7/00

CPC classification number: G11C7/22 ,  G11C7/02 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/50012

Abstract: A method of regulating timing of control signals in an integrated circuit memory device includes generating a pulse signal having a pulse width representing a time period between a rising edge of a first control signal and a rising edge of a second control signal that is activated after the first control signal. Based on the pulse width of the pulse signal, it is determined whether a timing margin between activation of the first control signal and activation of the second control signal is within a predetermined range, and the timing margin is adjusted responsive to the determination. For example, the pulse signal may be a timing measurement signal including a first pulse signal representing a first timing margin between a word line enable signal and a bit line sensing enable signal, a second pulse signal representing a second timing margin between a column select line enable signal and a first read pulse signal, and a third pulse signal representing a third timing margin between a word line disable signal and a bit line equalizing signal. Related devices are also discussed.

Abstract translation: 一种调节集成电路存储器件中的控制信号定时的方法包括：生成脉冲信号，该脉冲信号具有表示在第一控制信号的上升沿和第二控制信号的上升沿之间的时间周期的脉冲宽度， 第一控制信号。 基于脉冲信号的脉冲宽度，确定第一控制信号的激活和第二控制信号的激活之间的定时裕度是否在预定范围内，并且响应于该确定来调整定时裕度。 例如，脉冲信号可以是定时测量信号，其包括表示字线使能信号和位线检测使能信号之间的第一定时裕度的第一脉冲信号，表示列选择线之间的第二定时裕度的第二脉冲信号 使能信号和第一读取脉冲信号，以及表示字线禁止信号和位线均衡信号之间的第三定时裕度的第三脉冲信号。 还讨论了相关设备。

公开(公告)号：US07495472B2

公开(公告)日：2009-02-24

申请号：US11426040

申请日：2006-06-23

Applicant: Je-min Yu ,  Chi-wook Kim

Inventor： Je-min Yu ,  Chi-wook Kim

IPC: H03K19/173

CPC classification number: G11C17/18

Abstract: A fuse circuit can include a cut-off unit circuit configured to electrically isolate a fuse from an input to a status information circuit after latching of status information associated with status of the fuse. Other fuse related circuits and methods are disclosed.

Abstract translation: 保险丝电路可以包括截止单元电路，其被配置为在锁存与保险丝的状态相关联的状态信息之后将保险丝与输入电隔离到状态信息电路。 公开了其它熔丝相关电路和方法。

公开(公告)号：US06525988B2

公开(公告)日：2003-02-25

申请号：US09884774

申请日：2001-06-19

Applicant: Dong-ryul Ryu ,  Chi-wook Kim

Inventor： Dong-ryul Ryu ,  Chi-wook Kim

IPC: G11C800

CPC classification number: G11C7/222 ,  G11C7/22 ,  G11C8/18 ,  G11C2207/2227 ,  H03L7/0802 ,  H03L7/0812

Abstract: Clock generating circuits for a semiconductor memory device are provided. The clock generating circuits include a delay locked loop (DLL) circuit that generates an internal clock signal for the semiconductor memory device. A control circuit activates the delay locked loop circuit for a predetermined time when the semiconductor memory device transitions from a self refresh mode, in which the DLL circuit is deactivated, to a standby mode. The control circuit may also be configured to deactivate the DLL circuit when the semiconductor memory device transitions from a power down mode, in which the DLL circuit is activated, to the standby mode. The semiconductor memory device may be a dynamic random access memory device and the predetermined time may be a number of clock cycles of the internal clock signal. Methods for operating the same are also provided.

公开(公告)号：US07352636B2

公开(公告)日：2008-04-01

申请号：US11313722

申请日：2005-12-22

Applicant: Soo-bong Chang ,  Chi-wook Kim

Inventor： Soo-bong Chang ,  Chi-wook Kim

IPC: G11C5/14

CPC classification number: G11C5/145 ,  G11C11/406 ,  G11C11/4074 ,  G11C2211/4065

Abstract: In a boosted voltage generating circuit of a semiconductor memory device, an active kicker drive signal generating circuit generates an active kicker drive signal having a first pulse duration in response to a row active command, and generates the active kicker drive signal having a second pulse duration in response to a refresh command. An active kicker circuit is responsive to the active kicker drive signal to generate the boosted voltage. The second pulse duration may be greater than the first pulse duration, which makes it possible to improve the pumping efficiency of the boosted voltage in a refresh operation.

Abstract translation: 在半导体存储器件的升压电压产生电路中，有源icker驱动信号发生电路响应于行有效命令产生具有第一脉冲持续时间的有效icker驱动信号，并产生具有第二脉冲持续时间 响应刷新命令。 有源激光电路响应于激活的激光驱动信号以产生升压电压。 第二脉冲持续时间可以大于第一脉冲持续时间，这使得可以在刷新操作中提高升压电压的泵送效率。

公开(公告)号：US20070280033A1

公开(公告)日：2007-12-06

申请号：US11756750

申请日：2007-06-01

Applicant: Chi-wook Kim ,  Tai-young Ko

Inventor： Chi-wook Kim ,  Tai-young Ko

IPC: G11C29/00 ,  G11C7/00 ,  G11C8/00 ,  G11C7/02

CPC classification number: G11C7/22 ,  G11C7/02 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/50012

Abstract: A method of regulating timing of control signals in an integrated circuit memory device includes generating a pulse signal having a pulse width representing a time period between a rising edge of a first control signal and a rising edge of a second control signal that is activated after the first control signal. Based on the pulse width of the pulse signal, it is determined whether a timing margin between activation of the first control signal and activation of the second control signal is within a predetermined range, and the timing margin is adjusted responsive to the determination. For example, the pulse signal may be a timing measurement signal including a first pulse signal representing a first timing margin between a word line enable signal and a bit line sensing enable signal, a second pulse signal representing a second timing margin between a column select line enable signal and a first read pulse signal, and a third pulse signal representing a third timing margin between a word line disable signal and a bit line equalizing signal. Related devices are also discussed.

Abstract translation: 一种调节集成电路存储器件中的控制信号定时的方法包括：生成脉冲信号，该脉冲信号具有表示在第一控制信号的上升沿和第二控制信号的上升沿之间的时间周期的脉冲宽度， 第一控制信号。 基于脉冲信号的脉冲宽度，确定第一控制信号的激活和第二控制信号的激活之间的定时裕度是否在预定范围内，并且响应于该确定来调整定时裕度。 例如，脉冲信号可以是定时测量信号，其包括表示字线使能信号和位线检测使能信号之间的第一定时裕度的第一脉冲信号，表示列选择线之间的第二定时裕度的第二脉冲信号 使能信号和第一读取脉冲信号，以及表示字线禁止信号和位线均衡信号之间的第三定时裕度的第三脉冲信号。 还讨论了相关设备。

公开(公告)号：US20070002659A1

公开(公告)日：2007-01-04

申请号：US11426040

申请日：2006-06-23

Applicant: Je-min Yu ,  Chi-wook Kim

Inventor： Je-min Yu ,  Chi-wook Kim

IPC: G11C17/18

CPC classification number: G11C17/18

Abstract: A fuse circuit can include a cut-off unit circuit configured to electrically isolate a fuse from an input to a status information circuit after latching of status information associated with status of the fuse. Other fuse related circuits and methods are disclosed.

Abstract translation: 保险丝电路可以包括截止单元电路，其被配置为在锁存与保险丝的状态相关联的状态信息之后将保险丝与输入电隔离到状态信息电路。 公开了其它熔丝相关电路和方法。

公开(公告)号：US07057446B2

公开(公告)日：2006-06-06

申请号：US10726095

申请日：2003-12-02

Applicant: Jong-hyun Choi ,  Jae-hoon Kim ,  Jun-hyung Kim ,  Chi-wook Kim ,  Han-gu Sohn

Inventor： Jong-hyun Choi ,  Jae-hoon Kim ,  Jun-hyung Kim ,  Chi-wook Kim ,  Han-gu Sohn

IPC: G05F1/46 ,  G05F3/08

CPC classification number: G05F3/242

Abstract: Provided are a reference voltage generating circuit and an internal voltage generating circuit for controlling an internal voltage level, where the reference voltage generating circuit includes a distributing unit, a clamping control unit, and a control unit; the distributing unit has a voltage level lower than that of an external power supply voltage in response to the external power supply voltage, and outputs via an output terminal a reference voltage which varies according to an operating mode; the clamping control unit is connected between the output terminal and a ground voltage, and clamps the voltage level of the reference voltage at a constant level in response to a control voltage having a voltage level which is lower than that of the reference voltage; the control unit increases or decreases the voltage level of the reference voltage in response to first and second operating mode signals; the control unit includes a first control transistor and a second control transistor; and the reference voltage generating circuit controls a reference voltage level according to an operating mode of the semiconductor memory device such that the operating characteristics of the semiconductor memory device can be improved in some operating modes and power dissipation can be minimized in other operating modes.

Abstract translation: 提供了用于控制内部电压电平的基准电压发生电路和内部电压产生电路，其中基准电压发生电路包括分配单元，钳位控制单元和控制单元; 分配单元响应于外部电源电压具有低于外部电源电压的电压电平，并且经由输出端子输出根据操作模式而变化的参考电压; 所述钳位控制单元连接在所述输出端子和接地电压之间，并且响应于具有低于所述参考电压的电压电平的控制电压，将所述参考电压的电压电平钳位在恒定电平; 控制单元响应于第一和第二操作模式信号而增加或减小参考电压的电压电平; 所述控制单元包括第一控制晶体管和第二控制晶体管; 并且参考电压产生电路根据半导体存储器件的操作模式控制参考电压电平，使得可以在一些操作模式下改善半导体存储器件的工作特性，并且在其它操作模式中可以使功率损耗最小化。

公开(公告)号：US06795372B2

公开(公告)日：2004-09-21

申请号：US10389482

申请日：2003-03-14

Applicant: Myeong-o Kim ,  Chi-wook Kim ,  Sung-min Seo

Inventor： Myeong-o Kim ,  Chi-wook Kim ,  Sung-min Seo

IPC: G11C800

CPC classification number: G11C7/18 ,  G11C7/065 ,  G11C2207/065

Abstract: Bit line sense amplifier driving control circuits and methods for synchronous DRAMs selectively supply and suspend supply of operating voltages for bit line sense amplifiers. More specifically, a synchronous DRAM includes a memory cell array including at least a first column block and a second column block that are divided according to column address, first bit line sense amplifiers that are configured to sense data that is output from the first column block of the memory cell array, and second bit line sense amplifiers that are configured to sense data that is output from the second column block of the memory cell array. A bit line sense amplifier driving control circuit or method is responsive to a row address select signal, to supply an operating voltage to the first and second bit line sense amplifiers, and is responsive to a column select signal that selects a column address in the first column block, to suspend supplying an operating voltage to the second bit line sense amplifiers.

Abstract translation: 用于同步DRAM的位线读出放大器驱动控制电路和方法选择性地供给和暂停供给位线读出放大器的工作电压。 更具体地，同步DRAM包括存储单元阵列，该存储单元阵列至少包括根据列地址划分的第一列块和第二列块，第一位线读出放大器被配置为感测从第一列块输出的数据 以及被配置为感测从存储单元阵列的第二列块输出的数据的第二位线读出放大器。 位线读出放大器驱动控制电路或方法响应于行地址选择信号，向第一和第二位线读出放大器提供工作电压，并响应列选择信号，该列选择信号选择第一位 列块，以暂停向第二位线读出放大器提供工作电压。