公开(公告)号：US20210217850A1

公开(公告)日：2021-07-15

申请号：US16743584

申请日：2020-01-15

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Anthony K. STAMPER ,  Steven M. SHANK ,  John J. PEKARIK ,  Vibhor JAIN ,  John J. ELLIS-MONAGHAN

IPC: H01L29/16 ,  H01L21/02 ,  H01L27/12 ,  H01L21/762

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a wafer with crystalline silicon and trap rich polysilicon layer and methods of manufacture. The structure includes: semiconductor-on-insulator (SOI) wafer composed of a lower crystalline semiconductor layer, a polysilicon layer over the lower crystalline semiconductor layer, an upper crystalline semiconductor layer over the polysilicon layer, a buried insulator layer over the upper crystalline semiconductor layer, and a top crystalline semiconductor layer over the buried insulator layer.

公开(公告)号：US20230402453A1

公开(公告)日：2023-12-14

申请号：US18231510

申请日：2023-08-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor JAIN ,  John J. ELLIS-MONAGHAN ,  Anthony K. STAMPER ,  Steven M. SHANK ,  John J. PEKARIK

IPC: H01L27/082 ,  H01L27/06 ,  H01L29/737 ,  H01L29/06

CPC classification number: H01L27/082 ,  H01L27/0647 ,  H01L29/737 ,  H01L29/0646

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.

公开(公告)号：US20230299132A1

公开(公告)日：2023-09-21

申请号：US18324637

申请日：2023-05-26

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor JAIN ,  Anthony K. STAMPER ,  John J. ELLIS-MONAGHAN ,  Steven M. SHANK ,  Rajendran KRISHNASAMY

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/737 ,  H01L21/763 ,  H01L29/165

CPC classification number: H01L29/0642 ,  H01L29/0826 ,  H01L29/66242 ,  H01L29/7371 ,  H01L21/763 ,  H01L29/165

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.

公开(公告)号：US20220115549A1

公开(公告)日：2022-04-14

申请号：US17065862

申请日：2020-10-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Rajendran KRISHNASAMY ,  Steven M. SHANK ,  John J. ELLIS-MONAGHAN ,  Ramsey HAZBUN

IPC: H01L31/0352 ,  H01L31/0232 ,  H01L31/028 ,  H01L31/103 ,  H01L31/18

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a photodiode with an integrated, light focusing elements and methods of manufacture. The structure includes: a trench photodiode comprising a domed structure; and a doped material on the domed structure, the doped material having a concave underside surface.

公开(公告)号：US20210391489A1

公开(公告)日：2021-12-16

申请号：US16899028

申请日：2020-06-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Mark D. LEVY ,  Siva P. ADUSUMILLI ,  Vibhor JAIN ,  John J. ELLIS-MONAGHAN

IPC: H01L31/107 ,  H01L31/0352 ,  H01L31/18

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and/or PIN diode structures and methods of manufacture. The structure includes: at least one vertical pillar feature within a trench; a photosensitive semiconductor material extending laterally from sidewalls of the at least one vertical pillar feature; and a contact electrically connecting to the photosensitive semiconductor material.

公开(公告)号：US20210217849A1

公开(公告)日：2021-07-15

申请号：US16743589

申请日：2020-01-15

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Vibhor JAIN ,  Anthony K. STAMPER ,  Steven M. SHANK ,  John J. ELLIS-MONAGHAN ,  John J. PEKARIK

IPC: H01L29/10 ,  H01L27/12 ,  H01L29/78 ,  H01L21/74 ,  H01L21/84

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors with back gate contact and buried high resistivity layer and methods of manufacture. The structure includes: a handle wafer comprising a single crystalline semiconductor region; an insulator layer over the single crystalline semiconductor region; a semiconductor layer over the insulator layer; a high resistivity layer in the handle wafer, separated from the insulator layer by the single crystalline semiconductor region; and a device on the semiconductor layer.

公开(公告)号：US20210134987A1

公开(公告)日：2021-05-06

申请号：US16674432

申请日：2019-11-05

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Mankyu YANG ,  Jagar SINGH ,  Alexander MARTIN ,  John J. ELLIS-MONAGHAN

IPC: H01L29/735 ,  H01L29/417 ,  H01L29/06 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate controlled transistors and methods of manufacture. The structure includes: an emitter region; a collector region; base regions on opposing sides of the emitter region and the collector region; and a gate structure composed of a body region and leg regions, the body region being located between the base regions on opposing sides of the emitter region and the collector region, and the leg regions isolating the base regions from both the emitter region and the collector region.

公开(公告)号：US20220123107A1

公开(公告)日：2022-04-21

申请号：US17074891

申请日：2020-10-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor JAIN ,  Anthony K. STAMPER ,  John J. ELLIS-MONAGHAN ,  Steven M. SHANK ,  Rajendran KRISHNASAMY

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/737 ,  H01L29/165 ,  H01L21/763

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.

公开(公告)号：US20220093731A1

公开(公告)日：2022-03-24

申请号：US17028178

申请日：2020-09-22

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Anthony K. STAMPER ,  Siva P. ADUSUMILLI ,  Bruce W. PORTH ,  John J. ELLIS-MONAGHAN

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/764 ,  H01L21/762

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a semiconductor on insulator substrate with cavity structures and methods of manufacture. The structure includes: a bulk substrate with at least one rectilinear cavity structure; an insulator material sealing the at least one rectilinear cavity structure; and a buried insulator layer on the bulk substrate and over the at least one rectilinear cavity structure.

公开(公告)号：US20220068975A1

公开(公告)日：2022-03-03

申请号：US17003179

申请日：2020-08-26

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Siva P. ADUSUMILLI ,  Anthony K. STAMPER ,  Bruce W. PORTH ,  John J. ELLIS-MONAGHAN

IPC: H01L27/12 ,  H01L29/06 ,  H01L21/762

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a wafer with localized cavity structures and methods of manufacture. A structure includes a bulk substrate with localized semiconductor on insulator (SOI) regions and bulk device regions, the localized SOI regions includes multiple cavity structures and substrate material of the bulk substrate.