公开(公告)号：US20210384297A1

公开(公告)日：2021-12-09

申请号：US16893855

申请日：2020-06-05

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Henry L. ALDRIDGE, JR. ,  Anthony K. STAMPER ,  Jeonghyun HWANG ,  Johnatan A. KANTAROVSKY

IPC: H01L29/08 ,  H01L29/737 ,  H01L29/417 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a first semiconductor layer including a device region; a second semiconductor layer under the first semiconductor layer; a layer of conductive material between the first semiconductor layer and the second semiconductor layer; at least one contact extending to and contacting the layer of conductive material; and a device in the device region above the layer of conductive material.

公开(公告)号：US20240250157A1

公开(公告)日：2024-07-25

申请号：US18099366

申请日：2023-01-20

Applicant: GlobalFoundries U.S. Inc.

Inventor： Uppili S. RAGHUNATHAN ,  Vibhor JAIN ,  Yves T. NGU ,  Johnatan A. KANTAROVSKY ,  Sebastian T. VENTRONE

IPC: H01L29/73 ,  H01L23/34 ,  H01L27/07 ,  H01L29/06 ,  H01L29/08 ,  H01L29/737

CPC classification number: H01L29/7302 ,  H01L23/345 ,  H01L27/075 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heater terminal contacts, methods of operation and methods of manufacture. The structure includes: a heterojunction bipolar transistor having a collector, sub-collector region, emitter and base region; and heater terminal contacts electrically coupled to the sub-collector region.

公开(公告)号：US20240249992A1

公开(公告)日：2024-07-25

申请号：US18099389

申请日：2023-01-20

Applicant: GlobalFoundries U.S. Inc.

Inventor： Uppili S. RAGHUNATHAN ,  Vibhor JAIN ,  Yves T. NGU ,  Johnatan A. KANTAROVSKY ,  Sebastian T. VENTRONE

IPC: H01L23/34 ,  H01L29/737

CPC classification number: H01L23/345 ,  H01L29/7371

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heater elements, methods of operation and methods of manufacture. The structure includes: an active device; a heater element under the active device and within a semiconductor substrate; and a contact to the heater element and the active device.

公开(公告)号：US20230317627A1

公开(公告)日：2023-10-05

申请号：US17707273

申请日：2022-03-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Uppili S. RAGHUNATHAN ,  Vibhor JAIN ,  Siva P. ADUSUMILLI ,  Yves T. NGU ,  Johnatan A. KANTAROVSKY ,  Sebastian T. VENTRONE

IPC: H01L23/552 ,  H01L29/737 ,  H01L29/06 ,  H01L21/764

CPC classification number: H01L23/552 ,  H01L29/7371 ,  H01L29/0649 ,  H01L21/764

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with airgap structures and methods of manufacture. The structure includes: a semiconductor substrate with a trap-rich region; one or more airgap structures within the semiconductor substrate; at least one deep trench isolation structure laterally surrounding the one or more airgap structures and extending into the semiconductor substrate; and a device over the one or more airgap structures.

公开(公告)号：US20220320015A1

公开(公告)日：2022-10-06

申请号：US17223596

申请日：2021-04-06

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor JAIN ,  Yusheng BIAN ,  Yves T. NGU ,  Sunil K. SINGH ,  Sebastian T. VENTRONE ,  Johnatan A. KANTAROVSKY

IPC: H01L23/00

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a backside structure for optical attack mitigation and methods of manufacture. The structure includes: at least one device on a front side of a semiconductor substrate; and a plurality of grating layers under the at least one device. The plurality of grating layers includes at least a first material having a first refractive index alternating with a second material having a second refractive index.

公开(公告)号：US20220028971A1

公开(公告)日：2022-01-27

申请号：US16939213

申请日：2020-07-27

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Uzma RANA ,  Anthony K. STAMPER ,  Johnatan A. KANTAROVSKY ,  Steven M. SHANK ,  Siva P. ADUSUMILLI

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/762

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.