公开(公告)号：US20220028971A1

公开(公告)日：2022-01-27

申请号：US16939213

申请日：2020-07-27

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Uzma RANA ,  Anthony K. STAMPER ,  Johnatan A. KANTAROVSKY ,  Steven M. SHANK ,  Siva P. ADUSUMILLI

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/762

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.

公开(公告)号：US20210217849A1

公开(公告)日：2021-07-15

申请号：US16743589

申请日：2020-01-15

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Vibhor JAIN ,  Anthony K. STAMPER ,  Steven M. SHANK ,  John J. ELLIS-MONAGHAN ,  John J. PEKARIK

IPC: H01L29/10 ,  H01L27/12 ,  H01L29/78 ,  H01L21/74 ,  H01L21/84

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors with back gate contact and buried high resistivity layer and methods of manufacture. The structure includes: a handle wafer comprising a single crystalline semiconductor region; an insulator layer over the single crystalline semiconductor region; a semiconductor layer over the insulator layer; a high resistivity layer in the handle wafer, separated from the insulator layer by the single crystalline semiconductor region; and a device on the semiconductor layer.

公开(公告)号：US20240347528A1

公开(公告)日：2024-10-17

申请号：US18300161

申请日：2023-04-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya NATH ,  Rajendran KRISHNASAMY ,  Souvick MITRA ,  Steven M. SHANK ,  Sagar P. KARALKAR

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to silicon control rectifiers and methods of manufacture. A structure includes: a first well in a semiconductor substrate; a second well in the semiconductor substrate, adjacent to the first well; a plurality of shallow trench isolation structures extending into the first well and the second well; and at least one gate structure in the first well which abuts one shallow trench isolation structure of the plurality of shallow trench isolation structures.

公开(公告)号：US20220262900A1

公开(公告)日：2022-08-18

申请号：US17738179

申请日：2022-05-06

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Uzma RANA ,  Anthony K. STAMPER ,  Johnatan A. KANTAROVSKY ,  Steven M. SHANK ,  Siva P. ADUSUMILLI

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/763 ,  H01L29/10

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.

公开(公告)号：US20220199525A1

公开(公告)日：2022-06-23

申请号：US17126921

申请日：2020-12-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. STAMPER ,  John J. ELLIS-MONAGHAN ,  Steven M. SHANK ,  John J. PEKARIK ,  Vibhor JAIN

IPC: H01L23/525 ,  H01L27/12 ,  H01L23/532

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a metal-free fuse structure and methods of manufacture. The structure includes: a first metal-free fuse structure comprising a top semiconductor material of semiconductor-on-insulator (SOI) technologies, the top semiconductor material including end portions with a first electrical resistance and a fuse portion of a second, higher electrical resistance electrically connected to the end portions; and a second metal-free fuse structure comprising the top semiconductor material of semiconductor-on-insulator (SOI) technologies, the top semiconductor material of the second metal-free fuse structure including at least a fuse portion of a lower electrical resistance than the second, higher electrical resistance.

公开(公告)号：US20210313373A1

公开(公告)日：2021-10-07

申请号：US16842080

申请日：2020-04-07

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Siva P. ADUSUMILLI ,  Vibhor JAIN ,  Alvin J. JOSEPH ,  Steven M. SHANK

IPC: H01L27/146

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodetectors with buried airgap mirror reflectors. The structure includes a photodetector and at least one airgap in a substrate under the photodetector.

公开(公告)号：US20210202717A1

公开(公告)日：2021-07-01

申请号：US16730371

申请日：2019-12-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor JAIN ,  Steven M. SHANK ,  John J. PEKARIK ,  Anthony K. STAMPER

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L29/10 ,  H01L29/15 ,  H01L29/16 ,  H01L29/267

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistors with an oxygen lattice structure and methods of manufacture. The structure includes: a sub-collector region in a substrate; a collector region above the substrate; at least one oxygen film separating the sub-collector region and the collector region; an emitter region adjacent to the collector region; and a base region adjacent to the emitter region.

公开(公告)号：US20210159336A1

公开(公告)日：2021-05-27

申请号：US16691691

申请日：2019-11-22

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Anthony K. STAMPER ,  Aaron L. VALLETT ,  Steven M. SHANK ,  John J. ELLIS-MONAGHAN

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/45 ,  H01L29/417 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical field effect transistors (FETS) and methods of manufacture. The structure includes: a substrate material; at least one vertically oriented gate structure extending into the substrate material and composed of a gate dielectric material and conductive gate material; and vertically oriented source/drain regions extending into the substrate material and composed of conductive dopant material and a silicide on the source/drain regions.

公开(公告)号：US20240162116A1

公开(公告)日：2024-05-16

申请号：US17988335

申请日：2022-11-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva P. ADUSUMILLI ,  Mark D. LEVY ,  Steven M. SHANK

IPC: H01L23/473 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L23/473 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to structures with buried fluidic channels and methods of manufacture. The structure includes: a semiconductor substrate; a device layer with a gradient profile on the semiconductor substrate; a fluidic channel within the device layer comprising the gradient profile; at least one inlet channel in fluid communication with the fluidic channel; and at least one outlet channel in fluid communication with the fluidic channel.

公开(公告)号：US20220123107A1

公开(公告)日：2022-04-21

申请号：US17074891

申请日：2020-10-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor JAIN ,  Anthony K. STAMPER ,  John J. ELLIS-MONAGHAN ,  Steven M. SHANK ,  Rajendran KRISHNASAMY

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/737 ,  H01L29/165 ,  H01L21/763

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.