公开(公告)号：US20220216198A1

公开(公告)日：2022-07-07

申请号：US17704422

申请日：2022-03-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Souvick MITRA ,  Robert J. GAUTHIER, JR. ,  Alain F. LOISEAU ,  You LI ,  Tsung-Che TSAI

IPC: H01L27/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to diode triggered Silicon controlled rectifiers and methods of manufacture. The structure includes a diode string comprising a first type of diodes and a second type of diode in bulk technology in series with the diode string of the first type of diodes.

公开(公告)号：US20220059523A1

公开(公告)日：2022-02-24

申请号：US17001009

申请日：2020-08-24

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： You LI ,  Alain F. LOISEAU ,  Souvick MITRA ,  Tsung-Che TSAI ,  Robert J. GAUTHIER, JR. ,  Meng MIAO

IPC: H01L27/02 ,  H01L29/73

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an electrostatic discharge (ESD) device and methods of manufacture. The structure (ESD device) includes: a trigger collector region having fin structures of a first dopant type, a collector region having fin structures in a well of a second dopant type and further including a lateral ballasting resistance; an emitter region having a well of the second dopant type and fin structures of the first dopant type; and a base region having a well and fin structures of the second dopant type.

公开(公告)号：US20240339527A1

公开(公告)日：2024-10-10

申请号：US18296521

申请日：2023-04-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Judson R. HOLT ,  John J. PEKARIK ,  Anindya NATH ,  Souvick MITRA

IPC: H01L29/737 ,  H01L21/322

CPC classification number: H01L29/7371 ,  H01L21/322 ,  H01L29/747 ,  H01L29/78

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to low capacitance, low resistance devices and methods of manufacture. The structure includes: a semiconductor substrate; a device having an active region; and a porous semiconductor material within the semiconductor substrate and surrounding the active region of the device.

公开(公告)号：US20230420447A1

公开(公告)日：2023-12-28

申请号：US18462779

申请日：2023-09-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Robert J. GAUTHIER, JR. ,  Meng MIAO ,  Alain F. LOISEAU ,  Souvick MITRA ,  You LI ,  Wei LIANG

IPC: H01L27/02 ,  H01L21/84 ,  H01L21/8222 ,  H01L27/12

CPC classification number: H01L27/0259 ,  H01L27/0288 ,  H01L27/1207 ,  H01L21/8222 ,  H01L21/84

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure (ESD device) includes: a bipolar transistor comprising a collector region, an emitter region and a base region; and a lateral ballasting resistance comprising semiconductor material adjacent to the collector region.

公开(公告)号：US20230395591A1

公开(公告)日：2023-12-07

申请号：US17831545

申请日：2022-06-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anindya NATH ,  Souvick MITRA

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/66

CPC classification number: H01L27/0262 ,  H01L29/7412 ,  H01L29/66371

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertically stacked diode-trigger silicon controlled rectifiers and methods of manufacture. The structure includes: a silicon controlled rectifier in a trap rich region of a semiconductor substrate; and at least one diode built in polysilicon (gate material) and isolated by a gate-dielectric.

公开(公告)号：US20220271028A1

公开(公告)日：2022-08-25

申请号：US17185243

申请日：2021-02-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Robert J. GAUTHIER, JR. ,  Meng MIAO ,  Alain F. LOISEAU ,  Souvick MITRA ,  You LI ,  Wei LIANG

IPC: H01L27/02 ,  H01L27/12 ,  H01L21/8222 ,  H01L21/84

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure (ESD device) includes: a bipolar transistor comprising a collector region, an emitter region and a base region; and a lateral ballasting resistance comprising semiconductor material adjacent to the collector region.

公开(公告)号：US20220246749A1

公开(公告)日：2022-08-04

申请号：US17164855

申请日：2021-02-02

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Meng MIAO ,  Alain François LOISEAU ,  Souvick MITRA ,  Robert John GAUTHIER JR. ,  You LI ,  Wei LIANG

IPC: H01L29/74 ,  H01L29/06 ,  H01L29/66

Abstract: An ESD protection device may be provided, including: a substrate including a first conductivity region and a second conductivity region arranged therein. The first conductivity region may include a first terminal region and a second terminal region electrically coupled with each other. The second conductivity region may include a third terminal region and a fourth terminal region electrically coupled with each other. The second conductivity region may further include a fifth terminal region electrically coupled with the first and second terminal regions. The fifth terminal region may be arranged laterally between the third terminal region and the fourth terminal region. The first conductivity region, the first terminal region, the third terminal region, and the fifth terminal region may have a first conductivity type. The second conductivity region, the second terminal region, and the fourth terminal region may have a second conductivity type different from the first conductivity type.

公开(公告)号：US20210104512A1

公开(公告)日：2021-04-08

申请号：US16592013

申请日：2019-10-03

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Souvick MITRA ,  Alain F. LOISEAU ,  Robert J. GAUTHIER, JR. ,  You LI ,  Tsung-Che TSAI

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/747 ,  H01L29/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bi-directional silicon controlled rectifiers (SCRs) and methods of manufacture. The structure includes: a plurality of diffusion regions; a plurality of p-type (P+) wells adjacent to the diffusion regions, wherein the P+ wells are directly connected; and a plurality of n-type (N+) wells adjacent to the P+ wells.

公开(公告)号：US20240347528A1

公开(公告)日：2024-10-17

申请号：US18300161

申请日：2023-04-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya NATH ,  Rajendran KRISHNASAMY ,  Souvick MITRA ,  Steven M. SHANK ,  Sagar P. KARALKAR

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to silicon control rectifiers and methods of manufacture. A structure includes: a first well in a semiconductor substrate; a second well in the semiconductor substrate, adjacent to the first well; a plurality of shallow trench isolation structures extending into the first well and the second well; and at least one gate structure in the first well which abuts one shallow trench isolation structure of the plurality of shallow trench isolation structures.

公开(公告)号：US20240096874A1

公开(公告)日：2024-03-21

申请号：US17945348

申请日：2022-09-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya NATH ,  Alain F. LOISEAU ,  Souvick MITRA

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: The present disclosure relates to a structure including a trigger element within a semiconductor-on-insulator (SOI) substrate, and a silicon controlled rectifier (SCR) under a buried insulator layer of the SOI substrate. The trigger element is between an anode and a cathode of the SCR.