公开(公告)号：US20230343768A1

公开(公告)日：2023-10-26

申请号：US17992241

申请日：2022-11-22

Applicant: Google LLC

Inventor： Horia Alexandru Toma ,  Zuowei Shen ,  Hong Liu ,  Yujeong Shim ,  Biao He ,  Jaesik Lee ,  Georgios Konstadinidis ,  Teckgyu Kang ,  Igor Arsovski ,  Sukalpa Biswas

IPC: H01L25/16

CPC classification number: H01L25/167

Abstract: The technology generally relates to disaggregating memory from an application specific integrated circuit (“ASIC”) package. For example, a high-bandwidth memory (“HBM”) optics module package may be connected to an ASIC package via one or more optical links. The HBM optics module package may include HBM dies(s), HBM chiplet(s) and an optical chiplet. The optical chiplet may be configured to connect the HBM optics module to one or more optical fibers that form an optical link with one or more other components of the ASIC package. By including an optical chiplet in the HBM optics module package, the HBM optics module package may be disaggregated from an ASIC package.

公开(公告)号：US11249264B2

公开(公告)日：2022-02-15

申请号：US17122658

申请日：2020-12-15

Applicant: Google LLC

Inventor： William F. Edwards, Jr. ,  Melanie Beauchemin ,  Timothy Conrad Lee ,  Federico Pio Centola ,  Madhusudan K. Iyengar ,  Michael Chi Kin Lau ,  Zuowei Shen ,  Justin Sishung Lee

IPC: H04B10/00 ,  G02B6/42

Abstract: Heat dissipation and electric shielding techniques and apparatuses are disclosed to enable the operation of OSFP modules at higher bandwidths. OSFP compatible techniques are discussed including the use of water cooling, addition of heat pipes, use of intercoolers, air-fins and air-foils, optimization of cooling fins, use of vapor chambers are discussed.

公开(公告)号：US10905038B1

公开(公告)日：2021-01-26

申请号：US16688384

申请日：2019-11-19

Applicant: Google LLC

Inventor： Federico Pio Centola ,  Zuowei Shen ,  Xu Gao ,  Shawn Emory Bender ,  Melanie Beauchemin ,  Mark Villegas ,  Gregory Sizikov ,  Chee Yee Chung

IPC: H05K9/00

Abstract: An electromagnetic interference (“EMI”) sheet attenuator includes a planar conductive layer, a first flexible substrate and a second flexible substrate. The first flexible substrate overlies the metal backing layer and including a conductive pattern on a surface of the first flexible substrate. The second flexible substrate overlies the first flexible substrate and also includes the conductive pattern. The conductive pattern on the second flexible substrate is aligned with the conductive pattern on the first flexible substrate.