High bandwidth memory package for high performance processors

    公开(公告)号:US10658322B2

    公开(公告)日:2020-05-19

    申请号:US16698482

    申请日:2019-11-27

    申请人: Google LLC

    摘要: Integrated component packages and methods of assembling integrated component packages are provided. The integrated component package can comprise a bump pitch relaxing layer. A high-bandwidth memory component directly mechanically coupled to the bump pitch relaxing layer on a first side of the bump pitch relaxing layer via a first set of bump bond connections. The high-bandwidth memory component directly electrically coupled to the bump pitch relaxing layer on the first side of the bump pitch relaxing layer via the first set of bump bond connections. The bump pitch relaxing layer mechanically coupled to a first side of a substrate via second set of bump bond connections. The high-bandwidth memory component electrically coupled to the substrate via the bump-pitch relaxing layer and the second set of bump bond connections, and a bump pitch of the second set of bump bond connections is larger than the first set of bump bond connections.

    Cooling electronic devices in a data center

    公开(公告)号:US10548240B1

    公开(公告)日:2020-01-28

    申请号:US16246013

    申请日:2019-01-11

    申请人: Google LLC

    IPC分类号: H05K7/20 F28F3/02 H01L23/473

    摘要: A server tray package includes a motherboard assembly that includes a plurality of data center electronic devices; and a liquid cold plate assembly. The liquid cold plate assembly includes a base portion mounted to the motherboard assembly, the base portion and motherboard assembly defining a volume that at least partially encloses the plurality of data center electronic devices; and a top portion mounted to the base portion and including a heat transfer member that includes a first number of inlet ports and a second number of outlet ports that are in fluid communication with a cooling liquid flow path defined through the heat transfer member, the first number of inlet ports being different that the second number of outlet ports.

    Cooling electronic devices in a data center

    公开(公告)号:US10548239B1

    公开(公告)日:2020-01-28

    申请号:US16167905

    申请日:2018-10-23

    申请人: Google LLC

    IPC分类号: H05K7/20 H05K7/14

    摘要: A cooling system, for example, for rack mounted electronic devices (e.g., servers, processors, memory, networking devices or otherwise) in a data center. In various disclosed implementations, the cooling system may be or include a liquid cold plate assembly that is part of or integrated with a server tray package. In some implementations, the liquid cold plate assembly includes a base portion and a top portion that, in combination, form a cooling liquid flow path through which a cooling liquid is circulated and a thermal interface between one or more heat generating devices and the cooling liquid.

    Backside Integrated Voltage Regulator For Integrated Circuits

    公开(公告)号:US20220157787A1

    公开(公告)日:2022-05-19

    申请号:US17667104

    申请日:2022-02-08

    申请人: Google LLC

    IPC分类号: H01L25/065 H01L49/02

    摘要: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

    Backside integrated voltage regulator for integrated circuits

    公开(公告)号:US11276668B2

    公开(公告)日:2022-03-15

    申请号:US16788994

    申请日:2020-02-12

    申请人: Google LLC

    IPC分类号: H01L25/065 H01L49/02

    摘要: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.