公开(公告)号：US20050050188A1

公开(公告)日：2005-03-03

申请号：US10654139

申请日：2003-09-03

申请人： Gordon Davis ,  Marco Heddes ,  Dongming Hwang

发明人： Gordon Davis ,  Marco Heddes ,  Dongming Hwang

IPC分类号： G06F15/173 ,  G06F17/30

CPC分类号： G06F17/30955 ,  Y10S707/99933 ,  Y10S707/99942

摘要： A procedure is used to provide data structures that handle large numbers of active data entries and a high rate of additions and deletions of active entries. The procedure utilizes one or more of the following modifications. Timers are removed from individual session table entries and are linked via pointers. Bilateral links are established between the session table and the timer structure. Aging/timer checks are applied to the timer control block (TCB). A chain of TCBs, optionally including an excess of blocks, may be used along with packing of multiple TCBs into a single memory location. This excess of blocks permits a terminated session to continue to occupy a TCB until the timer process progresses to that block location in the chain of blocks.

摘要翻译： 一个过程用于提供处理大量活动数据条目的数据结构以及高活动条目的添加和删除率。 该过程利用以下一个或多个修改。 定时器从单个会话表条目中删除，并通过指针进行链接。 在会话表和定时器结构之间建立双向链路。 老化/定时器检查应用于定时器控制块（TCB）。 可以使用可选地包括多余块的TCB链，以及将多个TCB打包到单个存储器位置中。 这个多余的块允许终止的会话继续占用TCB，直到定时器进程前进到块链中的块位置。

公开(公告)号：US20050237939A1

公开(公告)日：2005-10-27

申请号：US10832958

申请日：2004-04-27

申请人： Everett Corl ,  Gordon Davis ,  Marco Heddes ,  Piyush Patel ,  Ravinder Sabhikhi

发明人： Everett Corl ,  Gordon Davis ,  Marco Heddes ,  Piyush Patel ,  Ravinder Sabhikhi

IPC分类号： G06F15/00 ,  G06F15/18 ,  G06F17/00 ,  G06N5/02 ,  G06N99/00 ,  H04J3/14 ,  H04L12/26 ,  G06N1/00

CPC分类号： G06N99/005

摘要： The present invention relates to a method and system for managing a plurality of multi-field classification rules. The method includes providing a first table that includes a plurality of entries corresponding to a plurality of rules relating to an ingress context and providing a second table that includes a plurality of entries corresponding to a plurality of rules relating to an egress context. The method also includes utilizing the first table and the second table to identify any rules relating to the ingress context and any rules relating to the egress context that match a search key.

摘要翻译： 本发明涉及一种用于管理多个多场分类规则的方法和系统。 该方法包括提供第一表格，该第一表格包括对应于与入口上下文有关的多个规则的多个条目，并提供第二表格，该第二表格包括对应于与出口上下文有关的多个规则的多个条目。 该方法还包括利用第一表和第二表来识别与入口上下文有关的任何规则以及与搜索关键字匹配的出口上下文相关的任何规则。

公开(公告)号：US20060265363A1

公开(公告)日：2006-11-23

申请号：US11457952

申请日：2006-07-17

申请人： Jean Calvignac ,  Gordon Davis ,  Marco Heddes ,  Michael Siegel

发明人： Jean Calvignac ,  Gordon Davis ,  Marco Heddes ,  Michael Siegel

IPC分类号： G06F17/30

CPC分类号： H04L49/3009 ,  G11C15/00 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/90

摘要： A method and system for identifying a data structure associated with a packet of data. A processor internal to a packet processor may extract one or more fields in a packet header field of a received packet of data to generate a search key. The internal processor may then be configured to select which table, e.g., routing table, quality of service table, filter table, needs to be accessed using the search key in order to process the received packet of data. A determination may then be made by the internal processor as to whether a CAM or a hash table and a Patricia Tree are used to identify the data structure associated with the received packet of data. Based on table definitions in a register, the internal processor may make such a determination.

摘要翻译： 一种用于识别与数据包相关联的数据结构的方法和系统。 分组处理器内部的处理器可以提取接收到的数据分组的分组报头字段中的一个或多个字段以生成搜索关键字。 然后可以将内部处理器配置为选择哪个表，例如路由表，服务质量表，过滤表，需要使用搜索关键字进行访问，以便处理接收的数据分组。 然后内部处理器可以确定CAM或散列表和Patricia Tree是否用于标识与所接收的数据分组相关联的数据结构。 根据寄存器中的表定义，内部处理器可以作出这样的确定。

公开(公告)号：US20050050018A1

公开(公告)日：2005-03-03

申请号：US10654502

申请日：2003-09-03

申请人： Claude Basso ,  Gordon Davis ,  Marco Heddes ,  Dongming Hwang ,  Colin Verrilli

发明人： Claude Basso ,  Gordon Davis ,  Marco Heddes ,  Dongming Hwang ,  Colin Verrilli

IPC分类号： G06F17/30

CPC分类号： G06F16/20

摘要： Dynamic data search structures are described that are capable of handling large numbers of active entries and a high rate of additions and deletions of active entries while complying with 2MSL requirements and providing precise time-out capabilities. A free queue which is integrated with the timing loop of session entries provides available sessions for new entries in the search structure and removes obsolete sessions from the tree. Multiples of such timing loops can be used to maintain multiple timing intervals. One such timing loop may contain soft entries still attached to the search structure but which are eligible to be removed and to be reused to accommodate new sessions. A spare buffer pool is also included in the data structure to add and remove buffers to maintain delays.

摘要翻译： 描述了能够处理大量活动条目的动态数据搜索结构，以及符合2MSL要求并提供精确超时能力的活动条目的增加和删除的高速率。 与会话条目的定时循环集成的空闲队列为搜索结构中的新条目提供可用会话，并从树中删除过时的会话。 这种定时循环的倍数可用于维持多个定时间隔。 一个这样的定时循环可以包含仍然附着到搜索结构但是有资格被移除并被重新使用以容纳新会话的软条目。 数据结构中还包括备用缓冲池，以添加和删除缓冲区以维持延迟。

公开(公告)号：US20060265552A1

公开(公告)日：2006-11-23

申请号：US11131582

申请日：2005-05-18

申请人： Gordon Davis ,  Thomas Genduso ,  Harold Kossman ,  Robert Todd

发明人： Gordon Davis ,  Thomas Genduso ,  Harold Kossman ,  Robert Todd

IPC分类号： G06F13/00

CPC分类号： G06F12/0862 ,  G06F12/10 ,  G06F12/1027 ,  G06F2212/6024 ,  G06F2212/6026

摘要： A prefetch mechanism using prefetch attributes is disclosed. In one aspect, an explicit request for data stored in a memory is provided, and a prefetch attribute in a page table entry associated with the explicit request is examined to determine whether to provide one or more prefetch requests based on the prefetch attribute. Another aspect includes determining dynamic prefetch attributes for use in prefetching data, in which prefetch attributes are adjusted based on memory access requests that target next sequential blocks of memory relative to the most recent previous access in a page of memory.

摘要翻译： 公开了一种使用预取属性的预取机制。 在一个方面，提供对存储在存储器中的数据的显式请求，并且检查与显式请求相关联的页表条目中的预取属性，以基于预取属性来确定是否提供一个或多个预取请求。 另一方面包括确定用于在预取数据中使用的动态预取属性，其中基于存储器访问请求来调整预取属性，所述存储器访问请求相对于存储器页面中最近的先前存取的下一个顺序存储块。

公开(公告)号：US20060039457A1

公开(公告)日：2006-02-23

申请号：US11237001

申请日：2005-09-28

申请人： Gordon Davis ,  Jeffrey Derby ,  Evangelos Eleftheriou ,  Sedat Oelcer ,  Malcolm Ware

发明人： Gordon Davis ,  Jeffrey Derby ,  Evangelos Eleftheriou ,  Sedat Oelcer ,  Malcolm Ware

IPC分类号： H04B1/38

CPC分类号： H04L25/028 ,  H04L27/2626 ,  H04M11/062 ,  Y02D50/44

摘要： A low power DSL modem transmitter, suitable for incorporation in integrated DSLAM server line cards, transmits full power physical frames which include a control channel and a data field when data is available for transmission and physical frames having only a control channel or a control channel and a low power synchronization field when data is not available for transmission. And a method for controlling the total power dissipated in the integrated DSLAM by selectively restricting the flow of data packets to the DSLs.

公开(公告)号：US20050188129A1

公开(公告)日：2005-08-25

申请号：US10783757

申请日：2004-02-20

申请人： Youseff Abdelilah ,  Bartholomew Blaner ,  Gordon Davis ,  Jeffrey Derby ,  Joseph Garvey ,  Malcolm Ware ,  Hua Ye

发明人： Youseff Abdelilah ,  Bartholomew Blaner ,  Gordon Davis ,  Jeffrey Derby ,  Joseph Garvey ,  Malcolm Ware ,  Hua Ye

IPC分类号： G06F3/00 ,  G06F13/28 ,  H04L29/06

CPC分类号： G06F13/28

摘要： A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.

摘要翻译： 一种用于促进数字间数字信号处理（DSP）数据通信的方法，计算机程序产品和系统。 直接存储器访问（DMA）控制器可以被配置为便于在耦合到DMA控制器的第一和第二DSP处理器核之间传输数据。 DMA控制器可以读取被称为“缓冲器描述符块”的数据结构来执行数据传送。 缓冲器描述符块可以存储指示要检索和存储数据的源地址和目的地址。 缓冲器描述符块还可以存储指示要传送的数据的大小的值，例如字节数。 然后，DMA控制器可以将位于第一DSP处理器核心中的源地址处的数据以从缓冲器描述符块指示的大小（例如，字节数）传送到第二DSP处理器核心中的目的地地址。

公开(公告)号：US20050080995A1

公开(公告)日：2005-04-14

申请号：US10685054

申请日：2003-10-14

申请人： Gordon Davis ,  Thomas Genduso

发明人： Gordon Davis ,  Thomas Genduso

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/12

CPC分类号： G06F12/126

摘要： A method and system for improving the performance of a cache. The cache may include a tag entry that identifies the previously requested address by the processor whose data was not located in the cache. If the processor requests that address a second time, then there is a significant probability that the address will be accessed again. When the processor requests the address identified by the tag entry a second time, the cache is updated by inserting the data located at that address and evicting the data located in the least recently used entry. In this manner, data will not be evicted from the cache unless there is a significant probability that the data placed in the cache will likely be accessed again. Hence, data may not be evicted in the cache by the processor and replaced with data that will not be reused, such as in an interrupt routine.

摘要翻译： 一种用于提高缓存性能的方法和系统。 缓存可以包括标识条目，其标识由数据未位于高速缓存中的处理器先前请求的地址。 如果处理器第二次请求该地址，则重新有可能再次访问该地址。 当处理器第二次请求由标签条目标识的地址时，通过插入位于该地址的数据并驱逐位于最近最少使用的条目中的数据来更新高速缓存。 以这种方式，除非存在可能再次访问缓存中的数据的重大概率，否则数据将不会从高速缓存中逐出。 因此，数据可能不会被处理器在高速缓存中驱逐，并且被替换为不被重用的数据，例如在中断程序中。

公开(公告)号：US20080010390A1

公开(公告)日：2008-01-10

申请号：US11856509

申请日：2007-09-17

申请人： Youseff Abdelilah ,  Bartholomew Blaner ,  Gordon Davis ,  Jeffrey Derby ,  Joseph Garvey ,  Malcolm Ware ,  Hua Ye

发明人： Youseff Abdelilah ,  Bartholomew Blaner ,  Gordon Davis ,  Jeffrey Derby ,  Joseph Garvey ,  Malcolm Ware ,  Hua Ye

IPC分类号： G06F3/00

CPC分类号： G06F13/28

摘要： A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.

公开(公告)号：US20070079106A1

公开(公告)日：2007-04-05

申请号：US11232773

申请日：2005-09-22

申请人： Gordon Davis

发明人： Gordon Davis

IPC分类号： G06F12/00 ,  G06F7/00

CPC分类号： G06F12/1018 ,  G06F2212/1044

摘要： A page table mechanism translates virtual addresses to real addresses. In a first aspect, page table entries are contained in equal-sized blocks, the entries within each block corresponding to contiguous pages of virtual address space. Preferably, the common high-order portion of the virtual address is contained in segments distributed among multiple page table entries of the block. In a second aspect, the virtual address indexes a binary tree definitional structure. Decode logic traverses a binary tree defined by the definitional structure by testing selective bits of the virtual address to reach a leaf of the binary tree, which defines the location of data defining the real address.

摘要翻译： 页表机制将虚拟地址转换为实际地址。 在第一方面，页表条目包含在等大小的块中，每个块内的条目对应于虚拟地址空间的连续页面。 优选地，虚拟地址的公共高阶部分包含在分块在块的多个表表项之间的段中。 在第二方面，虚拟地址索引二进制树定义结构。 解码逻辑遍历由定义结构定义的二叉树，通过测试虚拟地址的选择性位以到达二叉树的叶，该二叉树定义了定义实际地址的数据的位置。