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28 条记录 (耗时 0.036 秒)

    Pipeline for processing network packets
    11.
    发明授权
    Pipeline for processing network packets 有权
    用于处理网络数据包的流水线

    公开(公告)号：US07990867B1

    公开(公告)日：2011-08-02

    申请号：US11799860

    申请日：2007-05-03

    申请人： Eric R. Keller ,  Philip B. James-Roxby

    发明人： Eric R. Keller ,  Philip B. James-Roxby

    IPC分类号： G01R31/08

    CPC分类号： H04L69/161

    摘要： A pipeline is provided for processing network packets. The pipeline includes a look-ahead stage, an operation stage, an insert/remove stage, and an interleave stage. The look-ahead stage synchronizes two or more fields of a network packet. The operation stage modifies one or more of the fields of the network packet. The operation stage may modify state data and the fields of the network packet as a function of the state data and the fields. The insert/remove stage performs data insertion and removal at one or more fields of the network packet. The interleave stage ensures that the modified network packet follows rules for interleaving network packets. The look-ahead, operation, insert/remove, and interleave stages are generated from a textual language specification of the processing of the network packets by the pipeline.

    摘要翻译： 提供流水线来处理网络数据包。 流水线包括一个预览阶段，一个操作阶段，一个插入/去除阶段和一个交错阶段。 先行阶段同步网络数据包的两个或多个字段。 操作阶段修改网络包的一个或多个字段。 操作阶段可以根据状态数据和字段来修改状态数据和网络包的字段。 插入/删除阶段在网络数据包的一个或多个字段执行数据插入和删除。 交织阶段确保修改的网络分组遵循用于交织网络分组的规则。 通过流水线对网络数据包的处理的文本语言规范生成前瞻，操作，插入/删除和交错阶段。

    Method and system for generating a circuit design including a peripheral component connected to a bus
    13.
    发明授权
    Method and system for generating a circuit design including a peripheral component connected to a bus 有权
    用于产生包括连接到总线的外围组件的电路设计的方法和系统

    公开(公告)号：US06883147B1

    公开(公告)日：2005-04-19

    申请号：US10304471

    申请日：2002-11-25

    申请人： Jonathan B. Ballagh ,  Roger Brent Milne ,  Jeffrey D. Stroomer ,  Eric R. Keller ,  L. James Hwang ,  Philip B. James-Roxby

    发明人： Jonathan B. Ballagh ,  Roger Brent Milne ,  Jeffrey D. Stroomer ,  Eric R. Keller ,  L. James Hwang ,  Philip B. James-Roxby

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/505

    摘要： Method and system for generating an electronic circuit design. A first logic block is instantiated in the design in response to user input controls. The first logic block includes parameters that specify its interface requirements. Bus interface blocks, which are parameterizable to connect a logic block to a bus, are provided in a library. Bus interface blocks that connect the first logic block to the bus are instantiated in the design, and the bus interface blocks are parameterized in response to the requirements of, the first logic block. The bus interface blocks are connected to the first logic block in such a way that the first logic block is extended into a peripheral that can communicate with the bus.

    摘要翻译： 用于生成电子电路设计的方法和系统。 响应于用户输入控件，第一个逻辑块在设计中实例化。 第一个逻辑块包括指定其接口要求的参数。 在库中提供了可以将逻辑块连接到总线的总线接口块。 在设计中实例化了将第一个逻辑块连接到总线的总线接口块，并根据第一个逻辑块的要求对总线接口块进行参数化。 总线接口块以这样的方式连接到第一逻辑块，使得第一逻辑块被扩展到可以与总线通信的外设。

    Bootable integrated circuit device for readback encoding of configuration data
    14.
    发明授权
    Bootable integrated circuit device for readback encoding of configuration data 有权
    可引导集成电路设备，用于配置数据的回读编码

    公开(公告)号：US07689726B1

    公开(公告)日：2010-03-30

    申请号：US10956884

    申请日：2004-10-01

    申请人： Prasanna Sundararajan ,  Brandon J. Blodget ,  Scott P. McMillan ,  Philip B. James-Roxby ,  Eric R. Keller

    发明人： Prasanna Sundararajan ,  Brandon J. Blodget ,  Scott P. McMillan ,  Philip B. James-Roxby ,  Eric R. Keller

    IPC分类号： G06F3/00 ,  H03K19/173

    CPC分类号： H03K19/17764 ,  G06F9/4401 ,  H03K19/17768

    摘要： Method and apparatus for encoding configuration data is described. An integrated circuit device having a configuration interface is coupled to boot memory coupled at the configuration interface. The boot memory contains boot cores for configuring the integrated circuit device via the configuration interface. The boot cores include a configuration encoder core and an internal processor interface core. The boot cores may further include a processor core. The configuration encoder core provides a peripheral interface internal to the integrated circuit device, and the boot memory contains at least one set of instructions for encoding configuration data read from configuration memory. The encoded configuration data may be sent via the peripheral interface. Alternatively, configuration encoder core may include a configuration bitstream for instantiating an encoder in configurable resources for encoding readback configuration data.

    摘要翻译： 描述用于编码配置数据的方法和装置。 具有配置接口的集成电路装置耦合到在配置接口处耦合的引导存储器。 引导内存包含用于通过配置界面配置集成电路设备的引导内核。 引导核心包括配置编码器内核和内部处理器接口核心。 引导核心可以进一步包括处理器核心。 配置编码器核心提供集成电路设备内部的外围接口，并且引导存储器包含用于对从配置存储器读取的配置数据进行编码的至少一组指令。 编码的配置数据可以经由外设接口发送。 或者，配置编码器核心可以包括配置比特流，用于在用于编码回读配置数据的可配置资源中实例化编码器。

    Method for scheduling a network packet processor
    16.
    发明授权
    Method for scheduling a network packet processor 有权
    调度网络包处理器的方法

    公开(公告)号：US08284772B1

    公开(公告)日：2012-10-09

    申请号：US11799953

    申请日：2007-05-03

    申请人： Philip B. James-Roxby ,  Eric R. Keller

    发明人： Philip B. James-Roxby ,  Eric R. Keller

    IPC分类号： H04L12/28 ,  H04L12/56 ,  G06F13/00 ,  G06F13/28 ,  G06F9/30 ,  G06F9/40 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F3/00 ,  G06F9/45

    CPC分类号： G06F17/5045

    摘要： A method is provided for scheduling a network packet processor. A textual language specification is input of the processing of network packets by the network packet processor. The textual language specification includes memory read actions and modification actions. Each memory read action reads a stored value from a memory of the network packet processor. Each modification action modifies a field of the network packets. An availability is determined for each field read from the network packets for the memory read and modification actions. An availability is determined for each stored value read from the memory for the memory read actions. A look-ahead interval is determined from the availabilities. A respective storage class is determined for the fields for the memory read and modification actions. The respective storage class is one of a bus, a register, and a register with bypass.

    摘要翻译： 提供了一种用于调度网络分组处理器的方法。 文本语言规范是网络分组处理器对网络分组处理的输入。 文本语言规范包括内存读取操作和修改操作。 每个存储器读取动作从网络数据包处理器的存储器读取存储的值。 每个修改操作修改网络数据包的字段。 确定从网络数据包读取的每个字段的存储器读取和修改动作的可用性。 为存储器读取动作确定从存储器读取的每个存储值的可用性。 从可用性确定预先间隔。 为存储器读取和修改动作的字段确定相应的存储类别。 相应的存储类是总线，寄存器和旁路寄存器之一。

    Thread circuits and a broadcast channel in programmable logic
    17.
    发明授权
    Thread circuits and a broadcast channel in programmable logic 有权
    线程电路和可编程逻辑中的广播通道

    公开(公告)号：US07823162B1

    公开(公告)日：2010-10-26

    申请号：US11067431

    申请日：2005-02-25

    申请人： Eric R. Keller ,  Philip B. James-Roxby

    发明人： Eric R. Keller ,  Philip B. James-Roxby

    IPC分类号： G06F9/54 ,  G06F17/50

    CPC分类号： G06F17/5054

    摘要： Embodiments of a message processing circuit are disclosed. In one embodiment, a high-level language is used to specify a broadcast channel and first and second thread circuits. The first thread circuit outputs messages to the broadcast channel, each message having units of data, and starts the second thread circuit, indicating position in a message at which the second thread circuit is to commence reading data. The broadcast channel receives messages from the first thread circuit and outputs data of each message along with a position code indicating position in the message of current output data. The second thread reads data from the broadcast channel at a specified position in a message. The high-level language specification is translated into a hardware description language (HDL) specification, and the HDL specification is used to generate configuration data for programmable logic. Programmable logic is configured to implement the thread circuits and broadcast channel.

    摘要翻译： 公开了一种消息处理电路的实施例。 在一个实施例中，使用高级语言来指定广播频道以及第一和第二线程电路。 第一线程电路将消息输出到广播信道，每个消息具有数据单元，并且启动第二线程电路，指示第二线程电路开始读取数据的消息中的位置。 广播频道从第一线程电路接收消息，并输出每个消息的数据以及指示当前输出数据的消息中的位置的位置代码。 第二个线程在消息中的指定位置从广播频道读取数据。 高级语言规范被转换为硬件描述语言（HDL）规范，HDL规范用于生成可编程逻辑的配置数据。 可编程逻辑被配置为实现线程电路和广播信道。

    Method of using a hardware library in a programmable logic device
    18.
    发明授权
    Method of using a hardware library in a programmable logic device 有权
    在可编程逻辑器件中使用硬件库的方法

    公开(公告)号：US07028283B1

    公开(公告)日：2006-04-11

    申请号：US10354518

    申请日：2003-01-30

    申请人： Eric R. Keller ,  Philip B. James-Roxby

    发明人： Eric R. Keller ,  Philip B. James-Roxby

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054

    摘要： A method of using hardware libraries in a programmable logic device is disclosed. In particular, the method generally comprises steps of detecting a hardware library when compiling a software program for the programmable logic device; and accessing hardware module information stored in the hardware library; inserting the hardware module information of the hardware library into a reference platform.

    摘要翻译： 公开了一种在可编程逻辑器件中使用硬件库的方法。 特别地，该方法通常包括以下步骤：当编译可编程逻辑器件的软件程序时检测硬件库; 以及访问硬件库中存储的硬件模块信息; 将硬件库的硬件模块信息插入参考平台。

    Method and apparatus for configuring a processor embedded in an integrated circuit for use as a logic element
    19.
    发明授权
    Method and apparatus for configuring a processor embedded in an integrated circuit for use as a logic element 有权
    用于配置嵌入在集成电路中用作逻辑元件的处理器的方法和装置

    公开(公告)号：US07698449B1

    公开(公告)日：2010-04-13

    申请号：US11064148

    申请日：2005-02-23

    申请人： Eric R. Keller ,  Philip B. James-Roxby

    发明人： Eric R. Keller ,  Philip B. James-Roxby

    IPC分类号： G06F15/163

    CPC分类号： G06F15/7867 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30116 ,  G06F9/30134 ,  G06F9/325 ,  G06F9/383

    摘要： Method and apparatus for configuring a processor embedded in an integrated circuit for use as a logic element is described. In one example, a processing apparatus in an integrated circuit includes a point-to-point data streaming interface and arithmetic logic unit (ALU) circuitry. The ALU circuitry includes at least one input port in communication with the point-to-point data streaming interface. The processor may also include a register file and multiplexer logic. The multiplexer logic is configured to selectively couple the register file and the point-to-point streaming interface to the at least one input port of the ALU circuitry.

    摘要翻译： 描述用于配置嵌入在用于逻辑元件的集成电路中的处理器的方法和装置。 在一个示例中，集成电路中的处理装置包括点到点数据流接口和算术逻辑单元（ALU）电路。 ALU电路包括与点对点数据流接口通信的至少一个输入端口。 处理器还可以包括寄存器文件和多路复用器逻辑。 多路复用器逻辑被配置为选择性地将寄存器文件和点对点流接口耦合到ALU电路的至少一个输入端口。

    Memory arrangement for message processing by a plurality of threads
    20.
    发明授权
    Memory arrangement for message processing by a plurality of threads 有权
    用于多个线程的消息处理的存储器布置

    公开(公告)号：US07653895B1

    公开(公告)日：2010-01-26

    申请号：US11336211

    申请日：2006-01-20

    申请人： Philip B. James-Roxby ,  Eric R. Keller

    发明人： Philip B. James-Roxby ,  Eric R. Keller

    IPC分类号： G06F9/44

    CPC分类号： H04L69/12

    摘要： Various approaches for preparing a system for multi-thread processing of messages are disclosed. In one approach, respective portions of a message accessed by a plurality of threads are determined from a high-level language programming specification of the threads. A plurality of input elements are generated and respectively coupled to the plurality of threads. Each input element is configured to select from the message received by the input element the portion of the message accessed by the respective thread and provide each selected portion to the respective thread. A plurality of output elements are generated and configured with storage for data output by a respective thread. From a definition of an output message, a concentrator element is generated and is configured to read data from the output elements and assemble the data into an output message according to the definition of the output message.

    摘要翻译： 公开了用于准备用于消息的多线程处理的系统的各种方法。 在一种方法中，由线程的高级语言编程规范确定由多个线程访问的消息的相应部分。 生成多个输入元件并分别耦合到多个线程。 每个输入元件被配置为从由输入元件接收的消息中选择由相应线程访问的消息的部分，并将每个选择的部分提供给相应的线程。 生成多个输出元件并配置有用于由相应线程输出的数据的存储器。 根据输出消息的定义，生成集中器元件，并且被配置为从输出元件读取数据，并根据输出消息的定义将数据组合成输出消息。