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    Bootable integrated circuit device for readback encoding of configuration data
    2.
    发明授权
    Bootable integrated circuit device for readback encoding of configuration data 有权
    可引导集成电路设备，用于配置数据的回读编码

    公开(公告)号：US07689726B1

    公开(公告)日：2010-03-30

    申请号：US10956884

    申请日：2004-10-01

    申请人： Prasanna Sundararajan ,  Brandon J. Blodget ,  Scott P. McMillan ,  Philip B. James-Roxby ,  Eric R. Keller

    发明人： Prasanna Sundararajan ,  Brandon J. Blodget ,  Scott P. McMillan ,  Philip B. James-Roxby ,  Eric R. Keller

    IPC分类号： G06F3/00 ,  H03K19/173

    CPC分类号： H03K19/17764 ,  G06F9/4401 ,  H03K19/17768

    摘要： Method and apparatus for encoding configuration data is described. An integrated circuit device having a configuration interface is coupled to boot memory coupled at the configuration interface. The boot memory contains boot cores for configuring the integrated circuit device via the configuration interface. The boot cores include a configuration encoder core and an internal processor interface core. The boot cores may further include a processor core. The configuration encoder core provides a peripheral interface internal to the integrated circuit device, and the boot memory contains at least one set of instructions for encoding configuration data read from configuration memory. The encoded configuration data may be sent via the peripheral interface. Alternatively, configuration encoder core may include a configuration bitstream for instantiating an encoder in configurable resources for encoding readback configuration data.

    摘要翻译： 描述用于编码配置数据的方法和装置。 具有配置接口的集成电路装置耦合到在配置接口处耦合的引导存储器。 引导内存包含用于通过配置界面配置集成电路设备的引导内核。 引导核心包括配置编码器内核和内部处理器接口核心。 引导核心可以进一步包括处理器核心。 配置编码器核心提供集成电路设备内部的外围接口，并且引导存储器包含用于对从配置存储器读取的配置数据进行编码的至少一组指令。 编码的配置数据可以经由外设接口发送。 或者，配置编码器核心可以包括配置比特流，用于在用于编码回读配置数据的可配置资源中实例化编码器。

    Bootable programmable logic device for internal decoding of encoded configuration data
    4.
    发明授权
    Bootable programmable logic device for internal decoding of encoded configuration data 有权
    可引导可编程逻辑器件，用于编码配置数据的内部解码

    公开(公告)号：US07328335B1

    公开(公告)日：2008-02-05

    申请号：US10956989

    申请日：2004-10-01

    申请人： Prasanna Sundararajan ,  Brandon J. Blodget ,  Scott P. McMillan ,  Philip B. James-Roxby ,  Eric R. Keller

    发明人： Prasanna Sundararajan ,  Brandon J. Blodget ,  Scott P. McMillan ,  Philip B. James-Roxby ,  Eric R. Keller

    IPC分类号： G06F9/24

    CPC分类号： H03K19/17748 ,  G06F15/7867 ,  H03K19/17732 ,  H03K19/17768

    摘要： Method and apparatus for decoding configuration data is described. A programmable logic device having a configuration interface is coupled to boot memory coupled at the configuration interface. The boot memory contains boot cores for configuring the programmable logic device via the configuration interface. The boot cores include a configuration decoder core and an internal processor interface core. The boot cores may further include a processor core. The configuration decoder core provides a peripheral interface internal to the programmable logic device, and the boot memory contains at least one set of instructions for decoding encoded data and at least one library for writing decoded encoded data to configuration memory of the programmable logic device. The encoded data is obtained from data memory via the peripheral interface.

    摘要翻译： 描述用于解码配置数据的方法和装置。 具有配置接口的可编程逻辑器件耦合到在配置接口耦合的引导存储器。 引导内存包含用于通过配置界面配置可编程逻辑器件的引导内核。 引导核心包括配置解码器核心和内部处理器接口核心。 引导核心可以进一步包括处理器核心。 配置解码器核心提供可编程逻辑器件内部的外围接口，并且引导存储器包含用于解码编码数据的至少一组指令和用于将解码的编码数据写入可编程逻辑器件的配置存储器的至少一个存储库。 编码数据经由外围接口从数据存储器获得。

    Method and system for generating a bitstream view of a design
    6.
    发明授权
    Method and system for generating a bitstream view of a design 有权
    用于生成设计的比特流视图的方法和系统

    公开(公告)号：US07343578B1

    公开(公告)日：2008-03-11

    申请号：US10917064

    申请日：2004-08-12

    申请人： Cameron D. Patterson ,  Prasanna Sundararajan ,  Brandon J. Blodget ,  Scott P. McMillan

    发明人： Cameron D. Patterson ,  Prasanna Sundararajan ,  Brandon J. Blodget ,  Scott P. McMillan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： A method and system for generating a bitstream view of a programmable logic device (PLD) design are disclosed. The present invention allows for the correlation of a physical circuit description (e.g., one or more of a PLD design's essential configuration bits) and a logical circuit description (e.g., one or more of the logic elements that make up a PLD design), which can also be viewed as correlating one or more of the physical elements of the design's implementation in the PLD with one or more of the design's logical elements.

    摘要翻译： 公开了一种用于生成可编程逻辑器件（PLD）设计的位流视图的方法和系统。 本发明允许物理电路描述（例如，PLD设计的基本配置位中的一个或多个）与逻辑电路描述（例如，构成PLD设计的一个或多个逻辑元件）的相关性，其中 也可以被视为将PLD中设计实现的一个或多个物理元素与设计的一个或多个逻辑元素相关联。

    Methods of estimating susceptibility to single event upsets for a design implemented in an FPGA
    7.
    发明授权
    Methods of estimating susceptibility to single event upsets for a design implemented in an FPGA 有权
    估计在FPGA中实现的设计对单事件不匹配的敏感性的方法

    公开(公告)号：US07249010B1

    公开(公告)日：2007-07-24

    申请号：US10407280

    申请日：2003-04-03

    申请人： Prasanna Sundararajan ,  Carl H. Carmichael ,  Scott P. McMillan ,  Brandon J. Blodget ,  Cameron D. Patterson

    发明人： Prasanna Sundararajan ,  Carl H. Carmichael ,  Scott P. McMillan ,  Brandon J. Blodget ,  Cameron D. Patterson

    IPC分类号： G06F9/44 ,  G06F13/10 ,  G06F13/12 ,  G06F13/00 ,  G06F17/50 ,  G06F9/00 ,  G01R31/08 ,  G01F19/00 ,  G06F11/34 ,  G06F15/00 ,  G21C17/00 ,  H03K17/693 ,  H03K17/687

    CPC分类号： G06F17/5054 ,  G06F2217/70

    摘要： Methods of estimating the susceptibility to single event upsets (SEUs) of a design implemented in an FPGA. In an FPGA, many of the configuration memory cells could change state in response to an SEU without affecting the functionality of a design implemented in the FPGA. According to the methods of the invention, the number of “care bits” (bits associated with resources actually used in the design) is determined. The number of care bits as a proportion of the total number of configuration memory cells in the FPGA determines the “SEU Probability Impact” (SEUPI) value. The “Mean Time Between Upsets” (MTBU) value is an estimate of how much time will elapse, on average, before one of the configuration memory cells in the FPGA is affected by an SEU. To obtain the “Mean Time Between Failures” for the design implemented in the FPGA, the MTBU value is divided by the SEUPI value.

    摘要翻译： 估计在FPGA中实现的设计对单事件扰乱（SEU）的敏感性的方法。 在FPGA中，许多配置存储单元可以响应于SEU而改变状态，而不影响在FPGA中实现的设计的功能。 根据本发明的方法，确定“关心位”（与设计中实际使用的资源相关联的位）的数量。 保留位的数量占FPGA中配置存储单元总数的比例决定了“SEU概率影响”（SEUPI）值。 “平均平均故障间隔时间”（MTBU）值是在FPGA中的一个配置存储器单元受SEU影响之前平均估计经过多少时间。 为了获得FPGA中设计的“平均故障间隔时间”，MTBU值除以SEUPI值。

    Method and system for device-level simulation of a circuit design for a programmable logic device
    9.
    发明授权
    Method and system for device-level simulation of a circuit design for a programmable logic device 有权
    用于可编程逻辑器件的电路设计的器件级仿真的方法和系统

    公开(公告)号：US06922665B1

    公开(公告)日：2005-07-26

    申请号：US09757404

    申请日：2001-01-08

    申请人： Steven A. Guccione ,  Scott P. McMillan ,  Brandon J. Blodget

    发明人： Steven A. Guccione ,  Scott P. McMillan ,  Brandon J. Blodget

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5027 ,  G06F17/5022

    摘要： A method and system for simulating a circuit design for a programmable logic device (PLD) at the device level. The same configuration data that is used to configure a PLD is used to generate objects that represent configurable logic elements of the PLD. During simulation, events are generated based on changes in output signal states of the objects. Each event includes an input signal state and identifies an object to which the input signal is to be applied. Since configurable logic elements are simulated, for example, lookup tables, instead of logic gates, fewer events need to be generated and processed than in a conventional simulator. In another embodiment, the system supports an interface that allows tools to interface with the simulator in the same manner as the tools interface with a PLD.

    摘要翻译： 一种用于在器件级模拟可编程逻辑器件（PLD）的电路设计的方法和系统。 用于配置PLD的相同配置数据用于生成表示PLD的可配置逻辑元素的对象。 在仿真期间，根据对象输出信号状态的变化生成事件。 每个事件包括输入信号状态，并且识别输入信号要被施加到的对象。 由于模拟可配置的逻辑元件，例如，查找表而不是逻辑门，需要比传统的模拟器更少的事件被生成和处理。 在另一个实施例中，系统支持允许工具以与工具与PLD接口相同的方式与模拟器进行接口的接口。

    Controller arrangement for partial reconfiguration of a programmable logic device
    10.
    发明授权
    Controller arrangement for partial reconfiguration of a programmable logic device 有权
    用于部分重新配置可编程逻辑器件的控制器布置

    公开(公告)号：US06810514B1

    公开(公告)日：2004-10-26

    申请号：US10188510

    申请日：2002-07-03

    申请人： Peter H. Alfke ,  Scott P. McMillan ,  Brandon J. Blodget ,  Delon Levi

    发明人： Peter H. Alfke ,  Scott P. McMillan ,  Brandon J. Blodget ,  Delon Levi

    IPC分类号： G06F1750

    CPC分类号： G06F17/5054

    摘要： Method and apparatus for partial reconfiguration of a programmable logic device (PLD). In one embodiment, a configuration store is arranged for storage of configuration data for a selected subset of the reconfigurable resources of the PLD. A modification store is configured with addresses and associated data values. Each address in the modification store references an address in the configuration store, and each associated data value indicates a configuration state for one of the reconfigurable resources of the PLD. A controller is coupled to the configuration and modification stores and to the PLD. In response to a reconfiguration signal, the controller reads an address and associated data value from the modification store, updates the configuration store at the address read from the modification store with the associated data value, and downloads configuration data from the configuration store to the PLD.

    摘要翻译： 用于部分重新配置可编程逻辑器件（PLD）的方法和装置。 在一个实施例中，配置存储器被布置用于存储PLD的可重新配置资源的选定子集的配置数据。 修改存储配置有地址和关联的数据值。 修改存储器中的每个地址引用配置存储中的地址，并且每个相关联的数据值指示PLD的可重新配置资源之一的配置状态。 控制器耦合到配置和修改存储器以及PLD。 响应于重新配置信号，控制器从修改存储器读取地址和相关联的数据值，使用关联的数据值更新从修改存储器读取的地址处的配置存储，并将配置数据从配置存储器下载到PLD 。