公开(公告)号：US06892295B2

公开(公告)日：2005-05-10

申请号：US09802196

申请日：2001-03-08

申请人： Ashley Saulsbury

发明人： Ashley Saulsbury

IPC分类号： G06F9/30 ,  G06F9/345 ,  G06F9/355 ,  G06F9/38 ,  G06F7/02

CPC分类号： G06F9/30021 ,  G06F9/345 ,  G06F9/3842 ,  Y10T428/149

摘要： According to the invention, a method for processing data related to an array of elements is disclosed. In one embodiment, a method for processing data related to an array of elements is disclosed. In the process, a first value is loaded from a first location, and a second value is loaded from a second location. The first and second values are compared to each other. A predetermined value is optionally stored at a destination based upon the outcome of the comparison.

摘要翻译： 根据本发明，公开了一种用于处理与元件阵列有关的数据的方法。 在一个实施例中，公开了一种用于处理与元件阵列有关的数据的方法。 在该过程中，从第一位置加载第一值，并且从第二位置加载第二值。 将第一和第二值彼此进行比较。 基于比较的结果，可选地在目的地存储预定值。

公开(公告)号：US06631439B2

公开(公告)日：2003-10-07

申请号：US09802324

申请日：2001-03-08

申请人： Ashley Saulsbury ,  Nyles Nettleton ,  Michael Parkin

发明人： Ashley Saulsbury ,  Nyles Nettleton ,  Michael Parkin

IPC分类号： G06F1200

CPC分类号： G06F15/7857 ,  Y02D10/13

摘要： A novel processor chip (10) having a processing core (12), at least one bank of memory (14), an I/O link (26) configured to communicate with other like processor chips or compatible I/O devices, a memory controller (20) in electrical communication with processing core (12) and memory (14), and a distributed shared memory controller (22) in electrical communication with memory controller (20) and I/O link (26). Distributed shared memory controller (22) is configured to control the exchange of data between processor chip (10) and the other processor chips or I/O devices. In addition, memory controller (20) is configured to receive memory requests from processing core (12) and distributed shared memory controller (22) and process the memory request with memory (14). Processor chip (10) may further comprise an external memory interface (24) in electrical communication with memory controller (20). External memory interface (24) is configured to connect processor chip (10) with external memory, such as DRAM. Memory controller (20) is configured to receive memory requests from processing core (12) and distributed shared memory controller (22), determine whether the memory requests are directed to memory (14) on chip (10) or the external memory, and process the memory requests with memory (14) on processor chip (10) or with the external memory through external memory interface (24).

公开(公告)号：US07558816B2

公开(公告)日：2009-07-07

申请号：US09992064

申请日：2001-11-21

申请人： Ashley Saulsbury ,  Daniel S. Rice

发明人： Ashley Saulsbury ,  Daniel S. Rice

IPC分类号： G06F7/38

CPC分类号： H04N19/436 ,  H04N19/80

摘要： According to the invention, a process for averaging two pixel values is disclosed. In one step, an instruction is decoded. A plurality of first operands is loaded from a first input register. A plurality of second operands is loaded from a second input register. An average of one of the plurality of first operands and one of the plurality of second operands is produced. The average is stored in an output register.

摘要翻译： 根据本发明，公开了一种用于平均两个像素值的处理。 在一个步骤中，指令被解码。 从第一输入寄存器加载多个第一操作数。 从第二输入寄存器加载多个第二操作数。 产生多个第一操作数中的一个和多个第二操作数中的一个的平均值。 平均值存储在输出寄存器中。

公开(公告)号：US07124160B2

公开(公告)日：2006-10-17

申请号：US09801564

申请日：2001-03-08

申请人： Ashley Saulsbury ,  Daniel S. Rice

发明人： Ashley Saulsbury ,  Daniel S. Rice

IPC分类号： G06F7/38

CPC分类号： G06F7/505 ,  G06F7/49921 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30181 ,  G06F9/3851 ,  G06F9/3853 ,  G06F2207/382 ,  G06F2207/3828

摘要： According to the invention, a processing core is disclosed that includes a first source register, a number of second operands, a destination register, and a number of arithmetic processors. A bitwise inverter is coupled to at least one of the first number of operands and the second number of operands. The first source register includes a plurality of first operands and the destination register includes a plurality of results. The number of arithmetic processors are respectively coupled to the first operands, second operands and results, wherein each arithmetic processor computes one of a sum and a difference of the first operand and a respective second operand.

公开(公告)号：US06988181B2

公开(公告)日：2006-01-17

申请号：US09802289

申请日：2001-03-08

申请人： Ashley Saulsbury ,  Michael Parkin ,  Daniel S. Rice

发明人： Ashley Saulsbury ,  Michael Parkin ,  Daniel S. Rice

IPC分类号： G06F15/80

CPC分类号： G06F9/3891 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3012 ,  G06F9/30181 ,  G06F9/321 ,  G06F9/3828 ,  G06F9/3851 ,  G06F9/3865 ,  G06F9/3867 ,  G06F9/3885

摘要： According to the invention, a processing core is disclosed. The processing core includes one or more processing pipelines and a number of register flies. The processing pipelines having a total of N-number of processing paths, where each of the processing paths processes instructions on M-bit data words. Each of the number of register files has Q-number of registers that are each M-bits wide. The Q-number of registers within each of the plurality of register files are either private or global registers. When a value is written to one of said Q-number of said registers, which is a global register within one of said number of register files, the value is propagated to a corresponding global register in the other of the number of register files. When a value is written to one of said Q-number of the registers, which is a private register within one of said number of register files, the value is not propagated to a corresponding register in the other of said number of register files.

摘要翻译： 根据本发明，公开了一种处理核心。 处理核心包括一个或多个处理管道和多个寄存器蝇。 处理管道具有总共N个处理路径，其中每个处理路径处理关于M位数据字的指令。 每个寄存器文件的数量都是每个M位宽的Q个寄存器数。 多个寄存器文件的每一个内的寄存器的Q号是专用寄存器或全局寄存器。 当将值写入到所述寄存器文件数目之一中的全局寄存器的所述寄存器的所述Q号中的一个时，将该值传播到多个寄存器文件中的另一个中的对应的全局寄存器。 当将值写入到所述多个寄存器文件之一中的专用寄存器的所述Q号码之一时，该值不会传播到所述数量的寄存器文件中的另一个寄存器中。

公开(公告)号：US06314510B1

公开(公告)日：2001-11-06

申请号：US09291811

申请日：1999-04-14

申请人： Ashley Saulsbury ,  Daniel S. Rice

发明人： Ashley Saulsbury ,  Daniel S. Rice

IPC分类号： G06F9308

CPC分类号： G06F9/463 ,  G06F9/3832

摘要： A microprocessor with reduced context switching overhead and a corresponding method is disclosed. The microprocessor comprises a working register file that comprises dirty bit registers and working registers. The working registers including one or more corresponding working registers for each of the dirty bit registers. The microprocessor also comprises a decoder unit that is configured to decode an instruction that has a dirty bit register field specifying a selected dirty bit register of the dirty bit registers. The decoder unit is configured to generate decode signals in response. Furthermore, the working register file is configured to cause the selected dirty bit register to store a new dirty bit in response to the decode signals. The new dirty bit indicates that each operand stored by the one or more corresponding working registers is inactive and no longer needs to be saved to memory if a new context switch occurs.

摘要翻译： 公开了具有减少的上下文切换开销和相应方法的微处理器。 微处理器包括一个工作寄存器文件，其中包含脏位寄存器和工作寄存器。 工作寄存器包括一个或多个相应的工作寄存器，用于每个脏位寄存器。 微处理器还包括解码器单元，其被配置为对具有指定脏位寄存器的所选脏位寄存器的脏位寄存器字段的指令进行解码。 解码器单元被配置为响应地产生解码信号。 此外，工作寄存器文件被配置为使得所选择的脏位寄存器响应于解码信号存储新的脏位。 新的脏位表示由一个或多个对应的工作寄存器存储的每个操作数是不活动的，如果发生新的上下文切换，则不再需要将其保存到存储器中。

公开(公告)号：US06199142B1

公开(公告)日：2001-03-06

申请号：US08675254

申请日：1996-07-01

申请人： Ashley Saulsbury ,  Andreas Nowatzyk ,  Fong Pong

发明人： Ashley Saulsbury ,  Andreas Nowatzyk ,  Fong Pong

IPC分类号： G06F1300

CPC分类号： G06F12/0893 ,  G06F15/7821

摘要： An integrated processor/memory device comprising a main memory, a CPU, and a full width cache. The main memory comprises main memory banks. Each of the main memory banks stores rows of words. The rows are a predetermined number of words wide. The cache comprises cache banks. Each of the cache banks stores one or more cache lines of words. Each of the cache lines has a corresponding row in the corresponding main memory bank. The cache lines are the predetermined number of words wide. When the CPU issues an address in the address space of the corresponding main memory bank, the cache bank determines from the address and the tags of the cache lines whether a cache bank hit or a cache miss has occurred in the cache bank. When a cache bank miss occurs, the cache bank replaces a victim cache line of the cache lines with a new cache line that comprises the corresponding row of the corresponding memory bank specified by the issued address.

摘要翻译： 包括主存储器，CPU和全宽度高速缓存的集成处理器/存储器件。 主存储器包括主存储器。 每个主存储器组存储行的行。 行是预定数量的单词宽。 高速缓存包括缓存组。 每个缓存库存储一个或多个字的高速缓存行。 每个高速缓存行在相应的主存储体中具有相应的行。 高速缓存行是预定数量的单词宽。 当CPU在相应的主存储器的地址空间中发出地址时，高速缓存组从高速缓存行的地址和标签中确定高速缓存组中是否发生了高速缓存组命中或高速缓存未命中。 当发生缓存存储体未命中时，高速缓存组用新的高速缓存线代替高速缓存行的受害者高速缓存行，该高速缓存行包括由发布的地址指定的相应存储体的相应行。

公开(公告)号：US09106527B1

公开(公告)日：2015-08-11

申请号：US12976191

申请日：2010-12-22

申请人： Dana Cook ,  Chris Cole ,  David Nedde ,  Ashley Saulsbury

发明人： Dana Cook ,  Chris Cole ,  David Nedde ,  Ashley Saulsbury

IPC分类号： H04L12/24

CPC分类号： H04L41/08 ,  H04L41/0803 ,  H04L41/0813 ,  H04L41/0816 ,  H04L41/082 ,  H04L41/0843 ,  H04L41/0853

摘要： In one embodiment, an apparatus includes a network management module configured to execute at a network device operatively coupled to a switch fabric. The network management module is configured to receive a first set of configuration information associated with a subset of network resources from a set of network resources, the set of network resources being included in a virtual local area network from a plurality of virtual local area networks, the plurality of virtual local area networks being defined within the switch fabric. The first set of configuration information dynamically includes at least a second set of configuration information associated with the set of network resources.

摘要翻译： 在一个实施例中，一种装置包括网络管理模块，其被配置为在可操作地耦合到交换结构的网络设备处执行。 网络管理模块被配置为从一组网络资源接收与网络资源的子集相关联的第一组配置信息，该组网络资源被包括在来自多个虚拟局域网的虚拟局域网中， 多个虚拟局域网被定义在交换结构内。 第一组配置信息动态地包括与该组网络资源相关联的至少第二组配置信息。

公开(公告)号：US20070162625A1

公开(公告)日：2007-07-12

申请号：US11329656

申请日：2006-01-11

申请人： Ashley Saulsbury ,  David Redman ,  Gregory Onufer ,  John Johnson

发明人： Ashley Saulsbury ,  David Redman ,  Gregory Onufer ,  John Johnson

IPC分类号： G06F3/00

CPC分类号： G06F9/4411

摘要： A method and apparatus for delivering a device driver to an operating system without user intervention. One or more operating systems (e.g., different operating system programs, different versions of one operating system) execute on a computer platform. During booting of an operating system a device is identified for which a driver is needed. The driver is requested from a service processor of the platform, which includes memory or storage for storing multiple device drivers (or multiple versions of one driver, for different operating systems). The driver is retrieved from the service processor's storage and delivered to the operating system.

摘要翻译： 一种用于在没有用户干预的情况下将设备驱动程序传送到操作系统的方法和装置。 一个或多个操作系统（例如，不同的操作系统程序，一个操作系统的不同版本）在计算机平台上执行。 在启动操作系统期间，识别需要驱动程序的设备。 驱动程序是从平台的服务处理器请求的，其中包括用于存储多个设备驱动程序（或不同操作系统的一个驱动程序的多个版本）的存储器或存储器。 驱动程序从服务处理器的存储中检索并传送到操作系统。

公开(公告)号：US07191292B2

公开(公告)日：2007-03-13

申请号：US11144097

申请日：2005-06-02

申请人： Shailender Chaudhry ,  Quinn A. Jacobson ,  Ashley Saulsbury

发明人： Shailender Chaudhry ,  Quinn A. Jacobson ,  Ashley Saulsbury

IPC分类号： G06F12/00

CPC分类号： G06F11/165 ,  G06F11/141 ,  G06F11/1438

摘要： A plurality of processors on a chip is operated in lockstep. A crossbar switch on the chip couples and decouples the plurality of processors to a plurality of banks in a level-two (L2) cache. As data is stored in a first bank of the L2 cache, the old data at that location is passed through the crossbar switch to a second bank of the L2 cache that is functioning as a first-in-first-out memory (FIFO). Thus, new data is cached at a location in the first bank of the level-two cache, i.e., stored, and old data, from that location, is logged in the second bank of the level-two cache. The logged data in the second bank is used to restore the first bank to a known prior state when necessary.

摘要翻译： 芯片上的多个处理器在锁定状态下运行。 芯片上的交叉开关将多个处理器耦合并分离到二级（L2）高速缓存中的多个存储体。 当数据存储在L 2高速缓存的第一组中时，该位置处的旧数据通过交叉开关传递到作为先入先出存储器（FIFO）的L 2高速缓存的第二组 ）。 因此，新数据被缓存在二级高速缓存的第一组中的位置，即存储，并且来自该位置的旧数据被记录在二级高速缓存的第二组中。 当需要时，第二组中记录的数据用于将第一组恢复到已知的先前状态。