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    OPERAND FETCHING CONTROL AS A FUNCTION OF BRANCH CONFIDENCE
    11.
    发明申请
    OPERAND FETCHING CONTROL AS A FUNCTION OF BRANCH CONFIDENCE 有权
    操作控制作为分支机构的功能

    公开(公告)号：US20110320774A1

    公开(公告)日：2011-12-29

    申请号：US12822379

    申请日：2010-06-24

    申请人： Christian Jacobi ,  Barry W. Krumm ,  Brian R. Prasky ,  Martin Recktenwald ,  Chung-Lung K. Shum ,  Charles F. Webb ,  Joshua M. Weinberg

    发明人： Christian Jacobi ,  Barry W. Krumm ,  Brian R. Prasky ,  Martin Recktenwald ,  Chung-Lung K. Shum ,  Charles F. Webb ,  Joshua M. Weinberg

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3824 ,  G06F9/30043 ,  G06F9/3806 ,  G06F9/3844 ,  G06F9/3857

    摘要： A system for data operand fetching control includes a computer processor that includes a control unit for determining memory access operations. The control unit is configured to perform a method. The method includes calculating a summation weight value for each instruction in a pipeline, the summation weight value calculated as a function of branch uncertainty and a pendency in which the instruction resides in the pipeline relative to other instructions in the pipeline. The method also includes mapping the summation weight value of a selected instruction that is attempting to access system memory to a memory access control, each memory access control specifying a manner of handling data fetching operations. The method further includes performing a memory access operation for the selected instruction based upon the mapping.

    摘要翻译： 一种用于数据操作数取出控制的系统包括一计算机处理器，该计算机处理器包括用于确定存储器访问操作的控制 控制单元被配置为执行方法。 该方法包括：计算流水线中每个指令的求和权重值，求和作为分支不确定度的函数计算的求和权重值以及相对于流水线中的其他指令，指令驻留在流水线中的挂起。 该方法还包括将尝试访问系统存储器的所选择的指令的求和权重值映射到存储器访问控制，每个存储器访问控制指定处理数据获取操作的方式。 该方法还包括基于映射执行针对所选择的指令的存储器访问操作。

    Operand fetching control as a function of branch confidence
    12.
    发明授权
    Operand fetching control as a function of branch confidence 有权
    操作数获取控制作为分支置信度的函数

    公开(公告)号：US09411599B2

    公开(公告)日：2016-08-09

    申请号：US12822379

    申请日：2010-06-24

    申请人： Christian Jacobi ,  Barry W. Krumm ,  Brian R. Prasky ,  Martin Recktenwald ,  Chung-Lung K. Shum ,  Charles F. Webb ,  Joshua M. Weinberg

    发明人： Christian Jacobi ,  Barry W. Krumm ,  Brian R. Prasky ,  Martin Recktenwald ,  Chung-Lung K. Shum ,  Charles F. Webb ,  Joshua M. Weinberg

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3824 ,  G06F9/30043 ,  G06F9/3806 ,  G06F9/3844 ,  G06F9/3857

    摘要： Data operand fetching control includes a computer processor that includes a control unit for determining memory access operations. The control unit is configured to perform a method. The method includes calculating a summation weight value for each instruction in a pipeline, the summation weight value calculated as a function of branch uncertainty and a pendency in which the instruction resides in the pipeline relative to other instructions in the pipeline. The method also includes mapping the summation weight value of a selected instruction that is attempting to access system memory to a memory access control, each memory access control specifying a manner of handling data fetching operations. The method further includes performing a memory access operation for the selected instruction based upon the mapping.

    摘要翻译： 数据操作数获取控制包括计算机处理器，其包括用于确定存储器存取操作的控制单元。 控制单元被配置为执行方法。 该方法包括：计算流水线中每个指令的求和权重值，求和作为分支不确定度的函数计算的求和权重值以及相对于流水线中的其他指令，指令驻留在流水线中的挂起。 该方法还包括将尝试访问系统存储器的所选指令的求和权重值映射到存储器访问控制，每个存储器访问控制指定处理数据获取操作的方式。 该方法还包括基于映射执行针对所选择的指令的存储器访问操作。

    Combined Two-Level Cache Directory
    13.
    发明申请
    Combined Two-Level Cache Directory 审中-公开
    组合二级缓存目录

    公开(公告)号：US20140082252A1

    公开(公告)日：2014-03-20

    申请号：US13621465

    申请日：2012-09-17

    申请人： Khary J. Alexander ,  Jonathan T. Hsieh ,  Christian Jacobi ,  Barry W. Krumm

    发明人： Khary J. Alexander ,  Jonathan T. Hsieh ,  Christian Jacobi ,  Barry W. Krumm

    IPC分类号： G06F12/08 ,  G06F12/10

    CPC分类号： G06F12/0811 ,  G06F12/1054

    摘要： Responsive to receiving a logical address for a cache access, a mechanism looks up a first portion of the logical address in a local cache directory for a local cache. The local cache directory returns a set identifier for each set in the local cache directory. Each set identifier indicates a set within a higher level cache directory. The mechanism looks up a second portion of the logical address in the higher level cache directory and compares each absolute address value received from the higher level cache directory to an absolute address received from a translation look-aside buffer to generate a higher level cache hit signal. The mechanism compares the higher level cache hit signal to each set identifier to generate a local cache hit signal and responsive to the local cache hit signal indicating a local cache hit, accesses the local cache based on the local cache hit signal.

    摘要翻译： 响应于接收高速缓存访​​问的逻辑地址，机制在本地高速缓存目录中查找本地高速缓存的逻辑地址的第一部分。 本地缓存目录返回本地缓存目录中每个集合的集合标识符。 每个集合标识符表示较高级别的高速缓存目录中的集合。 该机制查找较高级别高速缓存目录中的逻辑地址的第二部分，并将从较高级别高速缓存目录接收的每个绝对地址值与从翻译后备缓冲器接收的绝对地址进行比较，以产生更高级别的高速缓存命中信号 。 该机制将高级缓存命中信号与每个集合标识符进行比较以产生本地高速缓存命中信号，并且响应于指示本地高速缓存命中的本地高速缓存命中信号，基于本地高速缓存命中信号访问本地高速缓存。

    Read only store as part of cache store for storing frequently used millicode instructions
    14.
    发明授权
    Read only store as part of cache store for storing frequently used millicode instructions 失效
    只读存储作为缓存存储的一部分，用于存储常用的millicode指令

    公开(公告)号：US5625808A

    公开(公告)日：1997-04-29

    申请号：US455820

    申请日：1995-05-31

    申请人： Charles F. Webb ,  Mark S. Farrell ,  Barry W. Krumm ,  John S. Liptay ,  Jennifer S. A. Navarro ,  Steven B. Risch ,  Mark A. Check

    发明人： Charles F. Webb ,  Mark S. Farrell ,  Barry W. Krumm ,  John S. Liptay ,  Jennifer S. A. Navarro ,  Steven B. Risch ,  Mark A. Check

    IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F9/22

    CPC分类号： G06F9/3802 ,  G06F9/3017

    摘要： A read only storage (ROS) array holds a small set of relatively simple millicode instructions; those millicode instruction routines which are most commonly called on in executing common application workloads. The millicode read only store is implemented as a portion of hardware system area (HSA) storage. The cache control includes a register which contains hardware system area address corresponding to the read only store address. When an instruction fetch request is received by the cache control, the absolute address of the instruction fetch request is compared with the read only store address in the register in parallel with the normal cache directory lookup. If the instruction fetch request matches the read only store address, the fetch is made from the read only store independently of the directory lookup result.

    摘要翻译： 只读存储（ROS）阵列包含一小组相对简单的millicode指令; 那些在执行常见应用程序工作负载中最常调用的那些millicode指令例程。 millicode只读存储器实现为硬件系统区域（HSA）存储的一部分。 高速缓存控制包括一个寄存器，该寄存器包含与只读存储地址对应的硬件系统区域地址。 当缓存控制接收到指令提取请求时，将指令提取请求的绝对地址与正常缓存目录查找并行地与寄存器中的只读存储地址进行比较。 如果指令提取请求与只读存储地址相匹配，则从独立于目录查找结果的只读存储进行读取。