公开(公告)号：US20200341898A1

公开(公告)日：2020-10-29

申请号：US16925870

申请日：2020-07-10

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Alexandros Daglis ,  Paolo Faraboschi ,  Qiong Cai ,  Gary Gostin

IPC: G06F12/0817 ,  G06F12/14 ,  G06F12/0831

Abstract: A technique includes, in response to a cache miss occurring with a given processing node of a plurality of processing nodes, using a directory-based coherence system for the plurality of processing nodes to regulate snooping of an address that is associated with the cache miss. Using the directory-based coherence system to regulate whether the address is included in a snooping domain is based at least in part on a number of cache misses associated with the address.

公开(公告)号：US20180203800A1

公开(公告)日：2018-07-19

申请号：US15746465

申请日：2015-07-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Alexandros Daglis ,  Paolo Fraboschi ,  Qiong Cai ,  Gary Gostin

IPC: G06F12/0817

CPC classification number: G06F12/0817 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/1441 ,  G06F12/1458 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/502

Abstract: A technique includes, in response to a cache miss occurring with a given processing node of a plurality of processing nodes, using a directory-based coherence system for the plurality of processing nodes to regulate snooping of an address that is associated with the cache miss. Using the directory-based coherence system to regulate whether the address is included in a snooping domain is based at least in part on a number of cache misses associated with the address.

公开(公告)号：US20180004674A1

公开(公告)日：2018-01-04

申请号：US15199285

申请日：2016-06-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Qiong Cai ,  Paolo Faraboschi

IPC: G06F12/0875

CPC classification number: G06F12/0875 ,  G06F9/46 ,  G06F12/0866 ,  G06F12/0893 ,  G06F2212/608

Abstract: Examples disclosed herein relate to programmable memory-side cache management. Some examples disclosed herein may include a programmable memory-side cache and a programmable memory-side cache controller. The programmable memory-side cache may locally store data of a system memory. The programmable memory-side cache controller may include programmable processing cores, each of the programmable processing cores configurable by cache configuration codes to manage the programmable memory-side cache for different applications.

公开(公告)号：US10922137B2

公开(公告)日：2021-02-16

申请号：US16073573

申请日：2016-04-27

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Qiong Cai ,  Charles Johnson ,  Paolo Faraboschi

IPC: G06F9/50 ,  G06F11/30 ,  G06F12/1027 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F9/52 ,  G06F12/0811

Abstract: In one example, a central processing unit (CPU) with dynamic thread mapping includes a set of multiple cores each with a set of multiple threads. A set of registers for each of the multiple threads monitors for in-flight memory requests the number of loads from and stores to at least a first memory interface and a second memory interface by each respective thread. The second memory interface has a greater latency than the first memory interface. The CPU further has logic to map and migrate each thread to respective CPU cores where the number of cores accessing only one of the at least first and second memory interfaces is maximized.

公开(公告)号：US10810492B2

公开(公告)日：2020-10-20

申请号：US15417760

申请日：2017-01-27

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Cong Xu ,  Qiong Cai

IPC: G06F3/06 ,  G06N3/08 ,  G06F13/16 ,  G06N3/04 ,  G06N3/063 ,  G06F9/48

Abstract: Examples disclosed herein relate to using a memory side accelerator to calculate updated deep learning parameters. A globally addressable memory includes deep learning parameters. The deep learning parameters are partitioned, where each partition is associated with a memory side accelerator. A memory side accelerator is to receive calculated gradient updates associated with its partition and calculate an update to the deep learning parameters associated with the partition.

公开(公告)号：US10282302B2

公开(公告)日：2019-05-07

申请号：US15199285

申请日：2016-06-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Qiong Cai ,  Paolo Faraboschi

IPC: G06F12/00 ,  G06F12/0875 ,  G06F12/0893 ,  G06F9/46 ,  G06F12/0866

Abstract: Examples disclosed herein relate to programmable memory-side cache management. Some examples disclosed herein may include a programmable memory-side cache and a programmable memory-side cache controller. The programmable memory-side cache may locally store data of a system memory. The programmable memory-side cache controller may include programmable processing cores, each of the programmable processing cores configurable by cache configuration codes to manage the programmable memory-side cache for different applications.

公开(公告)号：US20190095356A1

公开(公告)日：2019-03-28

申请号：US15718214

申请日：2017-09-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Dejan S. Milojicic ,  Moritz Josef Hoffmann ,  Alexander Richardson ,  Qiong Cai

IPC: G06F12/14 ,  G06F12/121 ,  G06F12/02

CPC classification number: G06F12/1441 ,  G06F12/023 ,  G06F12/121 ,  G06F2212/1052 ,  G06F2212/621

Abstract: In one example, a processor sends a memory access request including a data capability and a handle which references a master capability. In response to receiving the memory access request, a memory controller checks whether the handle references a valid master capability and checks whether the data capability is within a scope of the master capability. In response to determining that the master capability is valid and the data capability is within the scope of the master capability, the memory controller returns a result of the memory access request to the processor.

公开(公告)号：US20190034239A1

公开(公告)日：2019-01-31

申请号：US16073573

申请日：2016-04-27

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Qiong Cai ,  Charles Johnson ,  Paolo Faraboschi

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/52 ,  G06F12/0811

Abstract: In one example, a central processing unit (CPU) with dynamic thread mapping includes a set of multiple cores each with a set of multiple threads. A set of registers for each of the multiple threads monitors for in-flight memory requests the number of loads from and stores to at least a first memory interface and a second memory interface by each respective thread. The second memory interface has a greater latency than the first memory interface. The CPU further has logic to map and migrate each thread to respective CPU cores where the number of cores accessing only one of the at least first and second memory interfaces is maximized.