公开(公告)号：US20190237546A1

公开(公告)日：2019-08-01

申请号：US16198274

申请日：2018-11-21

Applicant: HRL Laboratories, LLC

Inventor： Biqin Huang ,  Xiwei Bai

IPC: H01L29/16 ,  H01L29/06 ,  H01L29/66 ,  H01L21/04 ,  H01L21/02 ,  H01L21/82

CPC classification number: H01L29/1602 ,  H01L21/02376 ,  H01L21/02603 ,  H01L21/0415 ,  H01L21/8206 ,  H01L29/0646 ,  H01L29/0669 ,  H01L29/66015

Abstract: A method for fabricating an electrically isolated diamond nanowire includes forming a diamond nanowire on a diamond substrate, depositing a dielectric or a polymer on the diamond nanowire and on the diamond substrate, planarizing the dielectric or the polymer, etching a portion of the planarized dielectric or polymer to expose a first portion of the diamond nanowire, depositing a metal layer to conformably cover the first portion of the diamond nanowire, and implanting ions into a second portion of the diamond nanowire between the first portion of the diamond nanowire and the diamond substrate or at an intersection of the diamond nanowire and the diamond substrate, wherein the ions are implanted at an oblique angle from a first side of the diamond nanowire.

公开(公告)号：US20190189791A1

公开(公告)日：2019-06-20

申请号：US16281727

申请日：2019-02-21

Applicant: HRL Laboratories, LLC

Inventor： Biqin Huang

IPC: H01L29/772 ,  H01L29/16 ,  H01L29/08 ,  H01L29/167 ,  H01L29/165 ,  H01L21/761 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7722 ,  H01L21/761 ,  H01L29/0646 ,  H01L29/0657 ,  H01L29/0673 ,  H01L29/0843 ,  H01L29/1029 ,  H01L29/16 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66045 ,  H01L29/66068 ,  H01L29/785 ,  H01L29/812

Abstract: Presented is a lateral fin static induction transistor including a semi conductive substrate, source and drain regions extending from an optional buffer layer of same or varied thickness supported by the semi conductive substrate, a semi conductive channel electrically coupling the source region to the drain region of the transistor, a portion of the semi conductive channel being a fin and having a face covered by a gated structure, thereby defining a gated channel within the semi conductive channel, the semi conductive channel further including a drift region electrically coupling the gated channel to the drain region of the transistor.