公开(公告)号：US12040362B2

公开(公告)日：2024-07-16

申请号：US16696039

申请日：2019-11-26

申请人： SHIN-ETSU CHEMICAL CO., LTD.

发明人： Hitoshi Noguchi

IPC分类号： H01L29/16 ,  C30B23/02 ,  C30B25/18 ,  C30B29/04 ,  C30B29/68 ,  H01L21/02 ,  H01L29/04 ,  B82Y30/00 ,  C30B29/02 ,  C30B29/16

CPC分类号： H01L29/1602 ,  C30B23/025 ,  C30B25/18 ,  C30B29/04 ,  C30B29/68 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02491 ,  H01L21/02527 ,  H01L21/02609 ,  H01L29/045 ,  B82Y30/00 ,  C30B29/02 ,  C30B29/16

摘要： A laminate substrate which includes a single crystal diamond (111) layer, including: an underlying substrate, an intermediate layer on the underlying substrate, and the single crystal diamond (111) layer on the intermediate layer, in which the underlying substrate has a main surface which has an off angle within a range, −8.0° or more and −0.5° or less, or +0.5° or more and +8.0° or less in a crystal axis [_1_1 2] direction or a threefold symmetry direction thereof relative to a crystal plane orientation of (111), and the single crystal diamond (111) layer has an off angle within a range, more than −10.5° and less than −2.0°, or more than +2.0° and less than +10.5° in the crystal axis [_1_1 2] direction or a threefold symmetry direction thereof relative to the crystal plane orientation of (111).

公开(公告)号：US12021468B2

公开(公告)日：2024-06-25

申请号：US16976593

申请日：2018-03-23

申请人： Mitsubishi Electric Corporation

发明人： Yuji Takayama ,  Haruka Matsuo ,  Kazunori Hatakeyama ,  Tomoyuki Kamiyama ,  Takuya Furuyama ,  Masami Yorita ,  Takanobu Kondo

IPC分类号： H02P27/08 ,  A47K10/48 ,  A47L5/24 ,  A47L9/28 ,  H02P27/04 ,  H01L29/16 ,  H01L29/20 ,  H01L29/78

CPC分类号： H02P27/085 ,  A47K10/48 ,  A47L5/24 ,  A47L9/2842 ,  A47L9/2894 ,  H02P27/045 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/7819

摘要： A motor drive device includes a single-phase inverter that converts a direct-current voltage into an alternating-current voltage applied to a motor. The motor drive device includes a control power supply outputting power having a voltage lower than the direct-current voltage. The motor drive device includes a drive signal generation unit driven by the power. The drive signal generation unit generates drive signals driving switching elements of the inverter. The motor drive device includes a power supply switch operating so as to allow supply of the power from the control power supply to the drive signal generation unit when a rotation speed of the motor is higher than a threshold. The power supply switch operates so as to stop the supply of the power from the control power supply to the drive signal generation unit when the rotation speed is lower than the threshold.

公开(公告)号：US12009213B2

公开(公告)日：2024-06-11

申请号：US17591384

申请日：2022-02-02

申请人： ROHM CO., LTD.

发明人： Yuki Nakano

IPC分类号： H01L29/861 ,  H01L21/02 ,  H01L21/04 ,  H01L21/28 ,  H01L27/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/872

CPC分类号： H01L21/049 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02241 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/044 ,  H01L21/28008 ,  H01L21/28264 ,  H01L27/04 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66045 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66446 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/8611 ,  H01L29/872 ,  H01L2224/0603

摘要： A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

公开(公告)号：US11984474B2

公开(公告)日：2024-05-14

申请号：US18182621

申请日：2023-03-13

申请人： II-VI Delaware, Inc.

发明人： Hossein Elahipanah

IPC分类号： H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/40 ,  H01L29/872

CPC分类号： H01L29/0619 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/404 ,  H01L29/872

摘要： There is disclosed a structure in a wide band gap material such as silicon carbide wherein there is a buried grid and shields covering at least one middle point between two adjacent parts of the buried grid, when viewed from above. Advantages of the invention include easy manufacture without extra lithographic steps compared with standard manufacturing process, an improved trade-off between the current conduction and voltage blocking characteristics of a JBSD comprising the structure.

公开(公告)号：US11942327B2

公开(公告)日：2024-03-26

申请号：US17659388

申请日：2022-04-15

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Aira Lourdes Villamor

IPC分类号： H01L21/00 ,  H01L21/304 ,  H01L29/16

CPC分类号： H01L21/3043 ,  H01L29/1602 ,  H01L29/1608

摘要： A method of singulating a silicon carbide (SiC) semiconductor wafer can include defining a cut within the silicon carbide (SiC) semiconductor wafer by performing a partial dicing operation where the SiC semiconductor wafer is aligned along a plane and the cut has a depth less than a first thickness of the SiC semiconductor wafer. The cut is aligned along a vertical direction orthogonal to the plane such that a portion of the SiC semiconductor wafer has a second thickness that extends between a bottom of the cut and an outer surface of the SiC semiconductor wafer. The method can further include defining a cleave, by performing a cleaving operation, through the portion of the SiC semiconductor wafer having the second thickness. The cleave can be aligned with the cut and extending to the outer surface of the SiC semiconductor wafer.

公开(公告)号：US11929394B2

公开(公告)日：2024-03-12

申请号：US17575148

申请日：2022-01-13

申请人： ROHM CO., LTD.

发明人： Yuki Nakano ,  Ryota Nakamura

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20 ,  H01L29/36 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L29/063 ,  H01L29/0619 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/4925 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7825 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/42376

摘要： A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.

公开(公告)号：US11798987B2

公开(公告)日：2023-10-24

申请号：US17421379

申请日：2020-01-08

申请人： PARCAN NANOTECH CO., LTD.

发明人： Ivo Rangelow ,  Xiang-Qian Zhou ,  Dimitre Karpuzov

IPC分类号： H01L29/06 ,  H01L21/265 ,  H01L21/266 ,  H01L29/16 ,  H01L29/66 ,  H01L29/861 ,  H01L29/868

CPC分类号： H01L29/0657 ,  H01L21/266 ,  H01L21/26506 ,  H01L29/1602 ,  H01L29/6603 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/868 ,  H01L29/8611 ,  H01L2021/26573

摘要： The present invention is related to a substrate (10) for a controlled implantation of ions (80) into a bulk (20), the substrate (10) comprising the bulk (20) composed of a crystalline first material (70), the bulk (20) comprising an implantation region (28) and a surface (22), wherein the implantation region (28) is located within the bulk (20) and along an implantation direction (82) at an implantation depth (26) below an implantation area (24) on the surface (10) of the bulk (20). Further, the present invention is related to a method of preparing a substrate (10) for a controlled implantation of ions (80) into a bulk (20), preferably the aforementioned substrate (10), the substrate (10) comprising the bulk (20) composed of a crystalline first material (70), the bulk (20) comprising an implantation region (28) and the surface (22), wherein the implantation region (28) is located within the bulk (20) and along an implantation direction (82) at an implantation depth (26) below an implantation area (24) on the surface (22) of the bulk (20).

公开(公告)号：US20230253510A1

公开(公告)日：2023-08-10

申请号：US18301899

申请日：2023-04-17

申请人： ROHM CO., LTD.

发明人： Masatoshi AKETA ,  Yuta YOKOTSUJI

IPC分类号： H01L29/872 ,  H01L29/06 ,  H01L29/861 ,  H01L29/08 ,  H01L29/16 ,  H01L29/20 ,  H01L23/535 ,  H01L29/36 ,  H01L29/66

CPC分类号： H01L29/872 ,  H01L29/0634 ,  H01L29/0623 ,  H01L29/0619 ,  H01L29/861 ,  H01L29/8613 ,  H01L29/08 ,  H01L29/1608 ,  H01L29/1602 ,  H01L29/2003 ,  H01L29/06 ,  H01L29/0607 ,  H01L23/535 ,  H01L29/0692 ,  H01L29/36 ,  H01L29/66143 ,  H01L29/8725 ,  H01L29/0615

摘要： The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage Vth of 0.3 V to 0.7 V and a leakage current Jr of 1×10−9 A/cm2 to 1×10−4 A/cm2 in a rated voltage VR.

公开(公告)号：US11652146B2

公开(公告)日：2023-05-16

申请号：US16897329

申请日：2020-06-10

申请人： RFHIC Corporation

发明人： Won Sang Lee

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L29/20 ,  H01L21/02 ,  H01L29/205 ,  H01L29/267 ,  H01L29/66 ,  H01L29/16 ,  H01L23/00

CPC分类号： H01L29/2003 ,  H01L21/0254 ,  H01L21/02378 ,  H01L21/02488 ,  H01L21/02527 ,  H01L21/76871 ,  H01L21/76897 ,  H01L24/94 ,  H01L29/1602 ,  H01L29/205 ,  H01L29/267 ,  H01L29/66462

摘要： Wafers including a diamond layer and a semiconductor layer having III-Nitride compounds and methods for fabricating the wafers are provided. A nucleation layer, at least one semiconductor layer having III-Nitride compound and a protection layer are formed on a silicon substrate. Then, a silicon carrier wafer is glass bonded to the protection layer. Subsequently the silicon substrate, nucleation layer and a portion of the semiconductor layer are removed. Then, an intermediate layer, a seed layer and a first diamond layer are sequentially deposited on the III-Nitride layer. Next, the silicon carrier wafer and the protection layer are removed. Then, a silicon substrate wafer that includes a protection layer, silicon substrate and a diamond layer is prepared and glass bonded to the first diamond layer.

公开(公告)号：US20190221651A1

公开(公告)日：2019-07-18

申请号：US16360775

申请日：2019-03-21

申请人： ROHM CO., LTD.

发明人： Yuki NAKANO

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/16 ,  H01L29/20 ,  H01L29/78 ,  H01L29/40

CPC分类号： H01L29/4236 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/66045 ,  H01L29/66068 ,  H01L29/66613 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7813

摘要： A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region.