-
公开(公告)号：US20240204807A1
公开(公告)日：2024-06-20
申请号：US18590534
申请日：2024-02-28
Applicant: Huawei Technologies Co., Ltd.
Inventor： Peng Gao
IPC: H04B1/00
CPC classification number: H04B1/0075 , H04B1/0064
Abstract: Embodiments of this application provide a wireless communication system and an electronic device. A first high-frequency integrated circuit in the wireless communication system includes a high-frequency control unit, a first diplexer, and a second diplexer. An intermediate-frequency integrated circuit includes an intermediate-frequency control unit, a third diplexer, and a fourth diplexer. A control signal is transmitted between the high-frequency control unit and the intermediate-frequency control unit. The control signal includes an instruction data signal and an echo clock signal. A phase of the instruction data signal is synchronized with a phase of the echo clock signal, and a frequency of the instruction data signal and a frequency of the echo clock signal are in a co-frequency relationship or a frequency multiplication relationship.
-
公开(公告)号：US20220216980A1
公开(公告)日：2022-07-07
申请号：US17705868
申请日：2022-03-28
Applicant: Huawei Technologies Co., Ltd.
Inventor： Peng Gao
IPC: H04L7/033
Abstract: Embodiments of this application disclose a wireless transceiver apparatus. The apparatus includes a radio frequency receiver, a radio frequency transmitter, a first serializer/deserializer, and a common clock phase-locked loop. The radio frequency receiver, the radio frequency transmitter, the first serializer/deserializer, and the common clock phase-locked loop are integrated in a radio frequency chip. The radio frequency receiver includes a down converter and an analog to digital converter. The radio frequency transmitter includes an up converter and a digital to analog converter. The first serializer/deserializer is configured to provide a serial digital interface with a baseband chip for the radio frequency chip. Coupled to the analog to digital converter, the digital to analog converter, and the first serializer/deserializer separately, the common clock phase-locked loop is configured to provide a clock signal for the analog to digital converter, the digital to analog converter, and the first serializer/deserializer.
-
13.发明申请公开(公告)号：US20220085821A1
公开(公告)日：2022-03-17
申请号：US17539149
申请日：2021-11-30
Applicant: HUAWEI TECHNOLOGIES CO.,LTD.
Inventor： Peng Gao
Abstract: A phase synchronization apparatus, a phase synchronization system, and a transceiver apparatus are disclosed to provide local oscillator signals with a same phase for each radio frequency transceiver chip in a multi-chip combination solution. The phase synchronization system includes a first radio frequency transceiver chip and a second radio frequency transceiver chip. The first radio frequency transceiver chip includes a first phase-locked loop and a first control circuit, and the second radio frequency transceiver chip includes a second phase-locked loop. The first phase-locked loop is configured to generate a first local oscillator signal, and the second phase-locked loop is configured to generate a second local oscillator signal.
-
公开(公告)号：US20210021525A1
公开(公告)日：2021-01-21
申请号：US17031855
申请日：2020-09-24
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Dayong Guo , Chenxi Hu , Peng Gao , Xindong Teng , Hongtao Guo , Shengtao Sun
IPC: H04L12/803 , H04L12/713 , H04L12/46 , H04L12/28 , G06F9/455 , H04L12/931
Abstract: Embodiments of the present invention disclose a virtual network device. The virtual network device is configured to implement a broadband network gateway BNG function, and the virtual network device includes a load balance unit and a first forwarding unit; the load balance unit is configured to: receive a first data packet from a first user terminal, determine the first forwarding unit according to the first data packet and a first correspondence, and send the first data packet to the first forwarding unit, where the first correspondence indicates mapping from the first user terminal to the first forwarding unit; and the first forwarding unit is configured to receive and forward the first data packet. In addition, the embodiments of the present invention further disclose a method for implementing load sharing in a virtual network device.
-
公开(公告)号：US10812394B2
公开(公告)日：2020-10-20
申请号：US16102745
申请日：2018-08-14
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Dayong Guo , Chenxi Hu , Peng Gao , Xindong Teng , Hongtao Guo , Shengtao Sun
IPC: G06F15/173 , H04L12/803 , H04L12/713 , H04L12/46 , H04L12/28 , G06F9/455 , H04L12/931 , H04L12/723
Abstract: Embodiments of the present invention disclose a virtual network device. The virtual network device is configured to implement a broadband network gateway BNG function, and the virtual network device includes a load balance unit and a first forwarding unit; the load balance unit is configured to: receive a first data packet from a first user terminal, determine the first forwarding unit according to the first data packet and a first correspondence, and send the first data packet to the first forwarding unit, where the first correspondence indicates mapping from the first user terminal to the first forwarding unit; and the first forwarding unit is configured to receive and forward the first data packet. In addition, the embodiments of the present invention further disclose a method for implementing load sharing in a virtual network device.
-
Patent Agency Ranking
公开(公告)号：US10419007B2
公开(公告)日：2019-09-17
申请号：US16169378
申请日：2018-10-24
Applicant: Huawei Technologies Co., Ltd.
Inventor： Peng Gao
Abstract: A digital frequency-division phase-locked loop, including a time-to-digital converter (TDC), a digital loop filter (DLF), a digital-controlled oscillator (DCO), a feedback frequency divider (DIV), a sigma-delta modulator (SDM), and a calibration apparatus, where the calibration apparatus compensates for, based on a frequency control word and a frequency-division control word generated by the SDM, a digital signal output by the TDC to obtain a calibration signal. The DLF performs digital filtering on the calibration signal to obtain an oscillator frequency control signal and set the oscillator frequency control signal as an output signal of the DCO.
-
公开(公告)号：US20240120632A1
公开(公告)日：2024-04-11
申请号：US18542619
申请日：2023-12-16
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Peng Gao , Xianlin Wei , Youbing Pan , Yi Xu
CPC classification number: H01P5/19 , H01P1/38 , H05K1/0243 , H05K1/115 , H01P3/08
Abstract: A coupler for use in a wireless communication device includes a signal input end, a signal output end, a coupling end, an isolation end, a main signal hole, and a first coupling hole disposed on a PCB. A first end of the main signal hole is coupled to the signal input end. A second end of the main signal hole is coupled to the signal output end. A first end of the first coupling hole is coupled to the coupling end. A second end of the first coupling hole is coupled to the isolation end. In a thickness direction of the PCB, the first end of the first coupling hole and the first end of the main signal hole are close to a first side of the PCB, and the second end of the first coupling hole and the second end of the main signal hole are close to a second side of the PCB.
-
公开(公告)号：US20220366030A1
公开(公告)日：2022-11-17
申请号：US17849307
申请日：2022-06-24
Applicant: Huawei Technologies Co., Ltd.
Inventor： Peng Gao
Abstract: A password management method and a related apparatus is provided. A TPM owner password is stored in a chip in a ciphertext form, so that security of the TPM owner password in a storage process can be improved. The method includes a chip encrypts a first TPM owner password by using a first key and a preset encryption algorithm, to obtain a first ciphertext corresponding to the first TPM owner password. After obtaining the first ciphertext, the chip stores the first ciphertext in a secure storage area in the chip.
-
公开(公告)号：US20210083699A1
公开(公告)日：2021-03-18
申请号：US17104732
申请日：2020-11-25
Applicant: Huawei Technologies Co., Ltd.
Abstract: A radio frequency transmitter includes a digital-to-analog converter, an analog baseband processor, and a modulator. The digital-to-analog converter is configured to convert a digital frequency-converted signal into a first analog signal, where the digital frequency-converted signal is obtained by performing digital frequency conversion on a digital baseband signal based on a first frequency signal; the analog baseband processor is configured to perform filtering and gain adjustment on the first analog signal to obtain a second analog signal; and the modulator is configured to perform up conversion based on a second frequency signal and the second analog signal, to obtain a radio frequency signal, where the second frequency signal is determined based on a local frequency signal and the first frequency signal.
-
20.发明申请公开(公告)号：US20170288686A1
公开(公告)日：2017-10-05
申请号：US15625449
申请日：2017-06-16
Applicant: Huawei Technologies Co., Ltd.
Inventor： Peng Gao
CPC classification number: H03L7/1974 , H03L7/081 , H03L7/085 , H03L7/091 , H03L7/0992 , H03L7/1976
Abstract: A method for controlling a digital fractional frequency-division phase-locked loop and a phase-locked loop are disclosed. The phase-locked loop includes a control apparatus, a TDC, a DLF, a DCO, a DIV, and an SDM. The control apparatus performs delay processing on an active edge of a reference clock according to a frequency control word and a frequency division control word to obtain a delayed reference clock; and sends the delayed reference clock to the TDC so that the TDC performs phase discrimination processing on the delayed reference clock and a feedback clock. A control apparatus added to a phase-locked loop may perform delay processing on a reference clock according to a current frequency control word and a current frequency division control word, so that a feedback clock and a delayed reference clock have active edges that approximately correspond in time.
-
-
-
-
-
-
-
-
-
Search Results
27
records
(took 0.02 seconds)
