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11.发明申请公开(公告)号：US20160248530A1
公开(公告)日：2016-08-25
申请号：US15142050
申请日：2016-04-29
Applicant: Huawei Technologies Co., Ltd.
Inventor： Liqing Chen , Tao Lin
IPC: H04J3/06 , H04L12/741 , H04L12/28 , H04L29/12
CPC classification number: H04J3/0667 , H04L12/2854 , H04L29/12575 , H04L45/745 , H04L61/6022 , H04L2012/5652
Abstract: Embodiments of the present invention disclose a WAN interface based 1588V2 packet transmission method and apparatus, which relate to the field of communications technologies and can reduce complexity of 1588V2 packet transmission. The method includes: first, inserting, by a sending end, a 1588V2 packet into a payload area of a data frame, and sending, to a receiving end, the data frame carrying the 1588V2 packet; then, receiving, by the receiving end, the data frame that is sent by the sending end and carries the 1588V2 packet, and acquiring a receiving time at which the data frame is received; and finally, performing, by the receiving end, time synchronization adjustment on the receiving time. The embodiments of the present invention are applicable to 1588V2 packet transmission between networks.
Abstract translation: 本发明的实施例公开了一种基于WAN接口的1588V2分组传输方法和装置，其涉及通信技术领域并且可以降低1588V2分组传输的复杂度。 该方法包括：首先，由发送端将1588V2分组插入数据帧的有效载荷区域，并向接收端发送携带1588V2分组的数据帧; 然后，由接收端接收发送端发送的数据帧并携带1588V2分组，并获取接收数据帧的接收时间; 最后，在接收端执行接收时间的时间同步调整。 本发明的实施例可应用于网络之间的1588V2分组传输。
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公开(公告)号：US20140093022A1
公开(公告)日：2014-04-03
申请号：US14098683
申请日：2013-12-06
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yongjie Shi , Tao Lin , Xiaodong Xu
IPC: H04L7/00
CPC classification number: H04L7/0012 , H04L7/10 , H04L41/0816 , H04L41/085 , H04L41/0866 , H04L41/0876 , H04L41/0896
Abstract: A method, a system, and an apparatus for dynamically adjusting a link, where the method includes: determining, by a transmitting end, link adjustment information according to the data traffic change when detecting a change of data traffic, where the link adjustment information contains the number of required working links; and adjusting, by the transmitting end, the number of working links on an interface of the transmitting end according to the determined link adjustment information, and sending a configuration request to a receiving end, where the configuration request includes the link adjustment information; and after receiving the configuration request, adjusting, by the receiving end, the number of working links on an interface of the receiving end according to the configuration request. In the embodiments of the present invention, data transmission on an original working link is not affected, thereby saving bandwidth and power consumption.
Abstract translation: 一种用于动态调整链路的方法，系统和装置，其中所述方法包括：当检测到数据业务的改变时，通过发送端确定根据数据流量变化的链路调整信息，其中链路调整信息包含 所需工作链接的数量; 以及根据确定的链路调整信息，通过发送端调整发送端的接口上的工作链路的数量，并且向接收端发送配置请求，其中配置请求包括链路调整信息; 并且在接收到所述配置请求之后，根据所述配置请求，在接收端调整所述接收端的接口上的工作链路的数量。 在本发明的实施例中，原始工作链路上的数据传输不受影响，从而节省带宽和功耗。
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公开(公告)号：US11824636B2
公开(公告)日：2023-11-21
申请号：US17833862
申请日：2022-06-06
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Xiang He , Yunlei Qi , Jingfeng Chen , Tao Lin , Junmin Song , Xinyuan Wang
IPC: H04J3/06 , H03M9/00 , H04J3/16 , H04L69/323
CPC classification number: H04J3/0667 , H03M9/00 , H04J3/0632 , H04J3/0688 , H04J3/1658 , H04L69/323
Abstract: This disclosure provides a method for sending and receiving a clock synchronization packet in FlexE. The method includes: generating, by a sending apparatus, indication information and a plurality of data blocks, where the plurality of data blocks are obtained by encoding a first clock synchronization packet, the indication information is used to indicate a first data block, and the first data block is a data block used for timestamp sampling in the plurality of data blocks; determining, by the sending apparatus, according to the indication information, a moment at which the first data block arrives at a medium dependent interface MDI of the sending apparatus, and generating a sending timestamp, where the sending timestamp is used to record a sending moment of the first clock synchronization packet; generating a second clock synchronization packet carrying the sending timestamp; and sending, by the sending apparatus, the second clock synchronization packet.
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公开(公告)号：US20230138058A1
公开(公告)日：2023-05-04
申请号：US18146634
申请日：2022-12-27
Applicant: Huawei Technologies Co., Ltd.
Inventor： Xiang He , Yunlei Qi , Jingfeng Chen , Tao Lin , Junmin Song , Xinyuan Wang
IPC: H04J3/06
Abstract: A clock synchronization method includes receiving, by a receiving apparatus, a plurality of data blocks using a plurality of physical layer modules (PHYs), where the plurality of data blocks include a plurality of head data blocks, performing, by the receiving apparatus, timestamp sampling on the plurality of data blocks to generate a plurality of receipt timestamps, aligning, by the receiving apparatus, the plurality of receipt timestamps using a first receipt timestamp as a reference, generating, by the receiving apparatus, a clock synchronization packet based on the plurality of data blocks, and writing, by the receiving apparatus, a value of a second receipt timestamp into the clock synchronization packet, where the second receipt timestamp is a receipt timestamp that is of a second data block and that is determined based on the plurality of aligned receipt timestamps.
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公开(公告)号：US11552721B2
公开(公告)日：2023-01-10
申请号：US17403131
申请日：2021-08-16
Applicant: Huawei Technologies Co., Ltd.
Inventor： Xiang He , Yunlei Qi , Jingfeng Chen , Tao Lin , Junmin Song , Xinyuan Wang
IPC: H04J3/06
Abstract: A clock synchronization method includes receiving, by a receiving apparatus, a plurality of data blocks using a plurality of physical layer modules (PHYs), where the plurality of data blocks include a plurality of head data blocks, performing, by the receiving apparatus, timestamp sampling on the plurality of data blocks to generate a plurality of receipt timestamps, aligning, by the receiving apparatus, the plurality of receipt timestamps using a first receipt timestamp as a reference, generating, by the receiving apparatus, a clock synchronization packet based on the plurality of data blocks, and writing, by the receiving apparatus, a value of a second receipt timestamp into the clock synchronization packet, where the second receipt timestamp is a receipt timestamp that is of a second data block and that is determined based on the plurality of aligned receipt timestamps.
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Patent Agency Ranking
公开(公告)号：US20200244383A1
公开(公告)日：2020-07-30
申请号：US16847258
申请日：2020-04-13
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Xiang He , Yunlei Qi , Jingfeng Chen , Tao Lin , Junmin Song , Xinyuan Wang
Abstract: This application provides a method for sending and receiving a clock synchronization packet in FlexE. The method includes: generating, by a sending apparatus, indication information and a plurality of data blocks, where the plurality of data blocks are obtained by encoding a first clock synchronization packet, the indication information is used to indicate a first data block, and the first data block is a data block used for timestamp sampling in the plurality of data blocks; determining, by the sending apparatus, according to the indication information, a moment at which the first data block arrives at a medium dependent interface MDI of the sending apparatus, and generating a sending timestamp, where the sending timestamp is used to record a sending moment of the first clock synchronization packet; generating a second clock synchronization packet carrying the sending timestamp; and sending, by the sending apparatus, the second clock synchronization packet.
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公开(公告)号：US09450886B2
公开(公告)日：2016-09-20
申请号：US14027931
申请日：2013-09-16
Applicant: Huawei Technologies Co., Ltd.
Inventor： Xueren Yang , Tao Lin , Jiehua Ye , Jianhua Zhou
IPC: H04L12/40 , H04L12/917 , G06F13/42
CPC classification number: H04L47/76 , G06F13/4295
Abstract: Embodiments of the present invention provide a bandwidth adjustment method, a bus controller, and a signal convertor. The method includes: obtaining, by a bus controller, a first frequency and a first channel number; sending a bandwidth negotiation request carrying the first frequency and the first channel number to a bus controller of a first peer end to determine whether or not the bus controller of the first peer end is capable of controlling a physical component of the first peer end to receive data via a channel corresponding to the first channel number according to the first frequency; and receiving a negotiation result sent by the first peer end and controlling the physical component to transmit data according to the negotiation result. In the technical solutions of the embodiments of the present invention, bandwidth adjustment is flexible and the loss of data is avoided.
Abstract translation: 本发明的实施例提供一种带宽调整方法，总线控制器和信号转换器。 该方法包括：由总线控制器获得第一频率和第一频道号码; 向第一对等端的总线控制器发送携带第一频率和第一频道号的带宽协商请求，以确定第一对等端的总线控制器是否能够控制第一对等端的物理组件接收 经由与第一频道号对应的频道的数据，根据第一频率; 以及接收由所述第一对等端发送的协商结果，并根据所述协商结果控制所述物理组件发送数据。 在本发明的实施例的技术方案中，带宽调整是灵活的，并且避免了数据丢失。
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公开(公告)号：US11843452B2
公开(公告)日：2023-12-12
申请号：US18146634
申请日：2022-12-27
Applicant: Huawei Technologies Co., Ltd.
Inventor： Xiang He , Yunlei Qi , Jingfeng Chen , Tao Lin , Junmin Song , Xinyuan Wang
IPC: H04J3/06
CPC classification number: H04J3/0661
Abstract: A clock synchronization method includes receiving, by a receiving apparatus, a plurality of data blocks using a plurality of physical layer modules (PHYs), where the plurality of data blocks include a plurality of head data blocks, performing, by the receiving apparatus, timestamp sampling on the plurality of data blocks to generate a plurality of receipt timestamps, aligning, by the receiving apparatus, the plurality of receipt timestamps using a first receipt timestamp as a reference, generating, by the receiving apparatus, a clock synchronization packet based on the plurality of data blocks, and writing, by the receiving apparatus, a value of a second receipt timestamp into the clock synchronization packet, where the second receipt timestamp is a receipt timestamp that is of a second data block and that is determined based on the plurality of aligned receipt timestamps.
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公开(公告)号：US11799576B2
公开(公告)日：2023-10-24
申请号：US17242929
申请日：2021-04-28
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Wenhua Du , Tao Lin , Min Chen , Feng Zhang
CPC classification number: H04J3/0605 , H04J3/1658
Abstract: This application discloses example data sending methods and apparatuses, and an example FlexE switching system. In one example, when slice packets received include a SOP flag and an EOP flag of a same data packet, immediately data packet slices is restored in the slice packets to a FlexE data stream and the FlexE data stream is sent, or the data packet slices are restored in the slice packets to the FlexE data stream and the FlexE data stream is sent when a latency is greater than or equal to a first present duration. When the slice packets received include the SOP flag but do not include the EOP flag of a data packet, the data packet slices are restored in the slice packets and the FlexE data stream is sent when the latency reaches a second preset duration. The first preset duration is less than the second preset duration.
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公开(公告)号：US11409118B2
公开(公告)日：2022-08-09
申请号：US16664409
申请日：2019-10-25
Inventor： Jia Jia , Jhensi Chen , Daping Chu , Qing Zhang , Tao Lin
IPC: G02B27/28 , G02B30/25 , G02B27/01 , G02F1/1335
Abstract: The present disclosure provides a device for generating a 3D light field. The device comprises a first lens having a fixed focal length, and an imaging element arranged to send light into the first lens. The imaging element is configured to send the light from different positions within a defined distance on the optical axis of the first lens, in order to produce different depth layers of the 3D light field within a frame duration.
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