公开(公告)号：US06778345B1

公开(公告)日：2004-08-17

申请号：US09503399

申请日：2000-02-14

Applicant: Hakan Ozdemir

Inventor： Hakan Ozdemir

IPC: G11B509

CPC classification number: G11B20/10055 ,  G11B5/012 ,  G11B20/10009 ,  G11B20/10027 ,  G11B20/10037 ,  G11B20/1403

Abstract: A circuit controls the gain of an amplifier that amplifies an information signal. The circuit includes a buffer that stores two samples of the amplified information signal, and includes a gain-determination circuit coupled to the buffer. The gain-determination circuit generates a gain adjustment that is based on the two samples and that causes the amplifier to shift the amplitude of the amplified information signal to or toward a predetermined amplitude. Such a circuit can provide an initial, coarse gain adjustment to a read-signal amplifier in a disk-drive read channel. Compared to prior read channels, this initial adjustment promotes faster settling of the amplifier gain at the beginning of a data sector. This faster settling allows the data sector to have a shorter preamble, and thus allows the disk to have a higher data-storage density. Furthermore, because the phase angle between the sample clock and the preamble sinusoid may be unknown at the beginning of the data sector, the circuit can determine the initial gain adjustment independent of this phase angle.

Abstract translation: 电路控制放大信号信号的放大器的增益。 该电路包括存储放大的信息信号的两个采样的缓冲器，并且包括耦合到缓冲器的增益确定电路。 增益确定电路产生基于两个采样的增益调整，并且使得放大器将放大的信息信号的幅度移动到或者朝向预定的幅度。 这样的电路可以在磁盘驱动器读取通道中为读取信号放大器提供初始的粗略增益调整。 与以前的读取通道相比，该初始调整可以促进在数据扇区开始时放大器增益的更快的建立。 这种更快的建立允许数据扇区具有较短的前导码，从而允许磁盘具有更高的数据存储密度。 此外，由于采样时钟与前导码正弦曲线之间的相位角在数据扇区的开始可能是未知的，所以电路可以独立于该相位角确定初始增益调整。

公开(公告)号：US06775084B1

公开(公告)日：2004-08-10

申请号：US09503453

申请日：2000-02-14

Applicant: Hakan Ozdemir ,  Jason D. Byrne

Inventor： Hakan Ozdemir ,  Jason D. Byrne

IPC: G11B502

CPC classification number: G11B20/10037 ,  G11B20/10009 ,  G11B20/1403 ,  H03L7/091

Abstract: A circuit includes a buffer for receiving and storing two samples of a signal, and a phase calculation circuit for calculating from the samples a phase difference between one of the samples and a predetermined point of the signal. Such a circuit can be used to decrease the alignment-acquisition time of a digital timing-recovery loop, and thus allows a shortening of the sector preambles and a corresponding increase in the data-storage density of a disk. In one application, the circuit determines an initial phase difference between a disk-drive read signal and a read-signal sample clock. The digital timing-recovery loop uses this phase difference to provide an initial coarse alignment between the read signal and the sample clock. By providing an initial coarse alignment, the recovery loop reduces the overall alignment-acquisition time.

Abstract translation: 电路包括用于接收和存储信号的两个采样的缓冲器，以及相位计算电路，用于从样本中计算一个采样之间的相位差和信号的预定点。 这样的电路可以用于减小数字定时恢复环路的对准采集时间，从而允许扇区前导码的缩短以及盘的数据存储密度的相应增加。 在一个应用中，电路确定磁盘驱动器读取信号和读取信号采样时钟之间的初始相位差。 数字定时恢复循环使用该相位差来提供读取信号和采样时钟之间的初始粗略对准。 通过提供初始粗略对准，恢复循环减少了整体对准采集时间。

公开(公告)号：US07839594B2

公开(公告)日：2010-11-23

申请号：US09993877

申请日：2001-11-05

Applicant: Hakan Ozdemir

Inventor： Hakan Ozdemir

IPC: G11B21/02

CPC classification number: G11B5/59633

Abstract: A data-storage disk includes a disk sector for storing data and a servo wedge located at the beginning of the sector. The servo wedge indentifies the sector in conjunction with both an initial positioning of a read-write head and a data read or write operation. By using a servo wedge to provide both an initial head position on disk spin up and a head position during a read or write operation, one can increase a disk's data-storage capacity by reducing the number of, or altogether eliminating, spin-up wedges.

Abstract translation: 数据存储盘包括用于存储数据的磁盘扇区和位于扇区开头的伺服楔。 伺服楔同时结合读写头的初始定位和数据读或写操作来识别扇区。 通过使用伺服楔以在读或写操作期间提供磁盘上升的初始头部位置和头部位置，可以通过减少旋转楔子的数量或完全消除磁盘的数据存储容量来增加磁盘的数据存储容量 。

公开(公告)号：US07430082B2

公开(公告)日：2008-09-30

申请号：US09993986

申请日：2001-11-05

Applicant: Fereidoon Heydari ,  Hakan Ozdemir

Inventor： Fereidoon Heydari ,  Hakan Ozdemir

IPC: G11B5/02 ,  G11B5/596

CPC classification number: G11B5/59655 ,  G11B5/59688

Abstract: A new technique for Hard Disk Drive (HDD) servo-burst demodulation is provided. A 4-samples per dibit Discrete Fourier Transform (DFT) amplitude estimation is used to calculate the read-head servo-position error signal. Comparatively, the conventional method of burst demodulation—called burst integration—typically uses more than 8 samples/dibit. Consequently, the new 4-samples/dibit DFT burst-demodulation scheme requires fewer samples per dibit than does burst integration, thus reducing the disk space occupied by the burst data while increasing the performance as compared to burst integration. Furthermore, the DFT scheme does not require the samples to be synchronized to any particular points of the servo burst, and can include an averaging algorithm that further improves performance for a given Signal to Noise Ratio (SNR). Moreover, the same sample-clocking circuit that detects the Gray Code servo information can also implement the DFT burst-demodulation scheme to demodulate the servo burst.

Abstract translation: 提供了一种用于硬盘驱动器（HDD）伺服突发解调的新技术。 使用4个样本每二进制离散傅里叶变换（DFT）幅度估计来计算读取头伺服位置误差信号。 相比之下，传统的突发解调方法 - 称为突发集成 - 通常使用多于8个采样/双位。 因此，新的4采样/双位DFT突发解调方案比突发集成需要比每比特少的采样，因此与突发集成相比，降低了突发数据占用的磁盘空间，同时提高了性能。 此外，DFT方案不要求样本与伺服脉冲串的任何特定点同步，并且可以包括进一步改善给定信噪比（SNR）的性能的平均算法。 此外，检测格雷码伺服信息的相同采样时钟电路还可以实现DFT突发解调方案来解调伺服脉冲串。

公开(公告)号：US06657800B1

公开(公告)日：2003-12-02

申请号：US09783801

申请日：2001-02-14

Applicant: Hakan Ozdemir ,  Jason D. Byrne ,  Fereidoon Heydari

Inventor： Hakan Ozdemir ,  Jason D. Byrne ,  Fereidoon Heydari

IPC: G11B509

CPC classification number: H03M13/6331 ,  G11B20/10009 ,  G11B20/1426 ,  H03M13/3961 ,  H03M13/41 ,  H03M13/6343

Abstract: A Viterbi detector receives a signal that represents a binary sequence having groups of no more and no fewer than a predetermined number of consecutive bits each having a first logic level, where the groups are separated from each other by respective bits having a second logic level. The Viterbi detector recovers the binary sequence from the signal by calculating a respective path metric for each of no more than four possible states of the binary sequence, and determining a surviving path from the calculated path metrics, where the binary sequence lies along the surviving path. Or, the Viterbi detector recovers the binary sequence from the signal by calculating respective path metrics for possible states of the binary sequence, calculating multiple path metrics for no more than one of the possible states, and determining the surviving path from the calculated path metrics.

Abstract translation: 维特比检测器接收表示具有不超过并且不小于预定数量的连续位的组的二进制序列的信号，每个连续位具有第一逻辑电平，其中通过具有第二逻辑电平的各个位彼此分离。 维特比检测器通过为二进制序列中不超过四个可能状态的每一个计算相应的路径度量，从信号中恢复二进制序列，以及从计算出的路径度量确定存活路径，其中二进制序列沿着存活路径 。 或者，维特比检测器通过计算二进制序列的可能状态的相应路径度量来计算来自信号的二进制序列，计算不超过一个可能状态的多个路径度量，以及根据计算的路径度量确定幸存路径。

公开(公告)号：US06604204B1

公开(公告)日：2003-08-05

申请号：US09410274

申请日：1999-09-30

Applicant: Hakan Ozdemir ,  Francesco Rezzi

Inventor： Hakan Ozdemir ,  Francesco Rezzi

IPC: H04L700

CPC classification number: H03M13/6343 ,  G11B20/16 ,  H03M13/41 ,  H03M13/4107 ,  H03M13/6502 ,  H04L7/041 ,  H04L7/042 ,  H04L7/046

Abstract: A synchronizer circuit includes an input terminal, an output terminal, and a recovery circuit coupled to the input and output terminals. The input terminal receives an input signal that includes a sync mark, and the recovery circuit is operable to recover the sync mark from the input signal and to generate a synchronization signal on the output terminal in response to the recovered synchronization mark. For example, such a synchronizer circuit can recover the synchronization mark from a read signal and locate the beginning of a data stream for a Viterbi detector that is separate from the circuit. By performing the sync-recovery function in a separate circuit, one can reduce the complexity and increase the data-recovery speed of the Viterbi detector. Furthermore, the synchronizer circuit can recover the sync mark by executing state-transition routines in alignment with the input signal. For example, one can align the synchronizer circuit's state-transition routines to the preamble of the read signal. Such alignment increases the circuit's noise immunity, and thus allows the circuit to recover the sync mark from a read signal having a SNR that is lower than the minimum read-signal SNR of prior sync-recovery circuits. Furthermore, such alignment reduces the time needed for the circuit to reliably detect the sync mark, and thus allows one to shorten the pad of the data forerunner.

Abstract translation: 同步器电路包括输入端子，输出端子和耦合到输入和输出端子的恢复电路。 输入端子接收包括同步标记的输入信号，并且恢复电路可操作以从输入信号中恢复同步标记，并响应于恢复的同步标记在输出端产生同步信号。 例如，这样的同步器电路可以从读取信号恢复同步标记，并定位与电路分离的维特比检测器的数据流的开始。 通过在单独的电路中执行同步恢复功能，可以降低维特比检测器的复杂度并提高数据恢复速度。 此外，同步器电路可以通过执行与输入信号对准的状态转换例程来恢复同步标记。 例如，可以将同步器电路的状态转换例程对准读取信号的前导码。 这种对准增加了电路的抗噪声能力，从而允许电路从具有低于先前同步恢复电路的最小读信号SNR的SNR的读信号中恢复同步标记。 此外，这种对准减少了电路可靠地检测同步标记所需的时间，并且因此允许缩短数据前端的焊盘。

公开(公告)号：US06246731B1

公开(公告)日：2001-06-12

申请号：US09126158

申请日：1998-07-30

Applicant: Francesco Brianti ,  Hakan Ozdemir

Inventor： Francesco Brianti ,  Hakan Ozdemir

IPC: H04L122

CPC classification number: G11B20/10175 ,  G11B20/10009 ,  G11B20/10055 ,  G11B20/10296

Abstract: Parallel processing in the form of two PR4 Viterbi Detectors connected in parallel operates to increase the maximum channel speed of a given data channel of a magnetic media. According to a target equation defined as Read(D)=(1−D2)2Written(D), in which D is the delay of a data of the channel, a first Viterbi Detector processes even data samples of the channel that have been equalized according to the target equation and a second Viterbi Detector connected in parallel processes odd data samples of the channel that have likewise been equalized according to the target equation. The use of two parallel-connected Viterbi Detectors in this fashion allows data to be processed at half-rate rather than full-rate, thereby increasing the overall channel speed.

Abstract translation: 并联连接的两个PR4维特比检测器的并行处理可以增加磁性介质给定数据通道的最大通道速度。 根据定义为Read（D）=（1-D2）2Written（D）的目标方程，其中D是信道的数据的延迟，第一维特比检测器处理已经被均衡的信道的均匀数据采样 根据目标方程和并行连接的第二维特比检测器处理根据目标方程同样被均衡的通道的奇数数据采样。 以这种方式使用两个并联连接的维特比检测器允许以半速率而不是全速率处理数据，从而增加总体通道速度。

公开(公告)号：US06201652B1

公开(公告)日：2001-03-13

申请号：US09087364

申请日：1998-05-29

Applicant: Francesco Rezzi ,  Hakan Ozdemir

Inventor： Francesco Rezzi ,  Hakan Ozdemir

IPC: G11B509

CPC classification number: G11B20/18 ,  G11B5/59616 ,  G11B5/59688 ,  G11B27/3027 ,  G11B2220/20

Abstract: A method for synchronously detecting servo information from a data disk includes reading servo information from a disk and passing the servo information signal through a Viterbi detector. The disk is encoded in a known data format from Gray code data to obtain a servo information signal, the encoded Gray code data being constrained to allow no more and no fewer than two “1” states to sequentially occur. The Viterbi detector is modified to eliminate state changes that do not occur within the constrained encoded Gray code data.

Abstract translation: 从数据盘同时检测伺服信息的方法包括从盘读取伺服信息并通过维特比检测器传递伺服信息信号。 磁盘以格雷码数据的已知数据格式进行编码以获得伺服信息信号，编码的格雷码数据被约束以允许不再有不少于两个“1”状态顺序发生。 维特比检测器被修改以消除在约束编码的格雷码数据内不发生的状态变化。

公开(公告)号：US07830630B2

公开(公告)日：2010-11-09

申请号：US09993779

申请日：2001-11-05

Applicant: Hakan Ozdemir

Inventor： Hakan Ozdemir

IPC: G11B5/09

CPC classification number: H03M7/16 ,  G11B20/10009 ,  G11B20/10055 ,  G11B20/10175 ,  G11B20/10222 ,  G11B20/10296 ,  G11B20/1403 ,  G11B20/18 ,  G11B2020/1282 ,  G11B2020/1284 ,  G11B2020/1484 ,  G11B2020/1859 ,  G11B2020/1863 ,  H03M13/41 ,  H03M13/6343

Abstract: A detector recovers servo data from a servo signal generated by a read-write head, and determines the head-connection polarity from the recovered servo data. Such a detector allows a servo circuit to compensate for a reversed-connected read-write head, and thus allows a manufacturer to forego time-consuming and costly testing to determine whether the head is correctly connected to the servo circuit.

Abstract translation: 检测器从由读写头产生的伺服信号中恢复伺服数据，并根据恢复的伺服数据确定磁头连接极性。 这种检测器允许伺服电路补偿反连接的读写头，并且因此允许制造商放弃耗时和昂贵的测试来确定磁头是否正确地连接到伺服电路。

公开(公告)号：US07346836B2

公开(公告)日：2008-03-18

申请号：US10194659

申请日：2002-07-12

Applicant: Hakan Ozdemir

Inventor： Hakan Ozdemir

IPC: H03M13/03

CPC classification number: G11B20/10064 ,  G11B20/10009 ,  H03M13/3961 ,  H03M13/4107 ,  H03M13/6343 ,  H03M13/6502

Abstract: An E2PR4 Viterbi detector receives a signal that represents a sequence of values, the sequence having a potential state. The detector includes a recovery circuit that recovers the sequence from the signal by identifying the surviving path to the potential state and simultaneously adding a modified branch metric to the path metric of the surviving path. By simultaneously identifying the surviving path and adding a modified branch metric to its path metric, such an E2PR4 Viterbi detector can operate faster than a conventional add-compare-select E2PR4 Viterbi detector.

Abstract translation: PR2维特比检测器接收表示值序列的信号，该序列具有潜在状态。 检测器包括恢复电路，其通过识别到潜在状态的幸存路径并且同时将修改的分支度量添加到幸存路径的路径度量来从信号恢复序列。 通过同时识别存活路径并将修改的分支度量添加到其路径度量，这样的第二维斯特维特比检测器可以比常规的加法比较选择E 2 SUP / > PR4维特比检测器。