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    Multi-directional wiring on a single metal layer
    11.
    发明授权
    Multi-directional wiring on a single metal layer 有权
    单一金属层上的多向布线

    公开(公告)号：US06858928B1

    公开(公告)日：2005-02-22

    申请号：US09733104

    申请日：2000-12-07

    申请人： Steven Teig ,  David Overhauser ,  Akira Fujimura

    发明人： Steven Teig ,  David Overhauser ,  Akira Fujimura

    IPC分类号： H01L23/528 ,  H01L23/12 ,  G06L9/45

    CPC分类号： H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit has a metal layer that includes conductors to provide interconnectivity for components of the integrated circuit chip. The metal layer is divided into at least two sections, such that a first section has a preferred direction and the second section has a preferred wiring direction that is different from the first preferred direction. The first and second preferred directions on a single metal layer may consist of any direction. The metal layer may be divided into more than two sections, wherein each section has a preferred wiring direction. Wiring geometries for multi-level metal layers are also disclosed.

    摘要翻译： 集成电路具有包括为集成电路芯片的组件提供互连的导体的金属层。 金属层被分成至少两个部分，使得第一部分具有优选的方向，并且第二部分具有不同于第一优选方向的优选的布线方向。 单个金属层上的第一和第二优选方向可由任何方向组成。 金属层可以被分成多于两个部分，其中每个部分具有优选的布线方向。 还公开了多层金属层的接线几何形状。

    Method and system for distributing clock signals on non-Manhattan semiconductor integrated circuits
    12.
    发明授权
    Method and system for distributing clock signals on non-Manhattan semiconductor integrated circuits 失效
    在非曼哈顿半导体集成电路上分配时钟信号的方法和系统

    公开(公告)号：US07644384B2

    公开(公告)日：2010-01-05

    申请号：US11464478

    申请日：2006-08-14

    申请人： Steven Teig ,  Raghu Chalasani ,  Akira Fujimura

    发明人： Steven Teig ,  Raghu Chalasani ,  Akira Fujimura

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  G06F1/10 ,  G06F2217/62

    摘要： The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal structure is rendered after transforming the coordinates system such that a rotated recursive H clock signal structure is rendered. In another embodiment, a recursive Y structure is used to create a clock signal structure. The recursive Y structure may also be implemented in a rotated alignment. For clock signal redundancy, non Manhattan wiring may be used to create a clock signal mesh network.

    摘要翻译： 本发明介绍了用于在集成电路布局中路由时钟信号的方法，系统和架构。 引入的时钟信号时钟信号结构以非曼哈顿路由呈现。 在第一实施例中，传统的递归H时钟信号结构在变换坐标系之后呈现，从而呈现旋转的递归H时钟信号结构。 在另一个实施例中，使用递归Y结构来创建时钟信号结构。 递归Y结构也可以以旋转的对准来实现。 对于时钟信号冗余，可以使用非曼哈顿布线来创建时钟信号网状网络。

    Circular vias and interconnect-line ends
    13.
    发明授权
    Circular vias and interconnect-line ends 失效
    圆形通孔和互连线端

    公开(公告)号：US06976238B1

    公开(公告)日：2005-12-13

    申请号：US10066094

    申请日：2002-01-31

    申请人： Steven Teig ,  Akira Fujimura ,  Andrew Caldwell

    发明人： Steven Teig ,  Akira Fujimura ,  Andrew Caldwell

    IPC分类号： G06F17/50 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528

    CPC分类号： G06F17/5068 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Some embodiments of the invention provide vias that are not in shape of quadrilaterals. In some embodiments, some or all vias are in shape of non-quadrilateral polygons, such as octagons and hexagons. In some embodiments, some or all vias have a circular shape. Some embodiments provide a first set of vias that have a diamond shape and a second set of vias that have a rectangular shape. In some embodiments, a via can also be formed by a diamond contact and a rectangular contact. The diamond contact has four sides. In the embodiments described below, all four sides of a diamond via contact have equal sides. However, in other embodiments, a via contact can be in shape of a diamond with a pair of sides that are longer than the other pair of sides. Similarly, in the embodiments described below, the rectangular via contacts are squares with four equal sides. However, in other embodiments, the length and width of a rectangular via contact can differ. Some embodiments of the invention provide interconnect lines that have non-rectangular ends. In some embodiments, the interconnect-line ends are partial octagons, hexagons, and/or circles. Also, some embodiments provide Steiner points that are not rectangular. In some embodiments, the Steiner points are octagonal, hexagonal, or circles.

    摘要翻译： 本发明的一些实施例提供不具有四边形形状的通孔。 在一些实施例中，一些或所有通孔的形状为非四边形多边形，例如八边形和六边形。 在一些实施例中，一些或所有通孔具有圆形形状。 一些实施例提供具有菱形形状的第一组通孔和具有矩形形状的第二组通孔。 在一些实施例中，也可以通过金刚石触点和矩形触点形成通孔。 钻石接触有四面。 在下面描述的实施例中，钻石经过接触的所有四个侧面具有相等的边。 然而，在其他实施例中，通孔接触可以是具有比另一对侧长的一对侧面的菱形的形状。 类似地，在下面描述的实施例中，矩形通孔触点是具有四个相等边的正方形。 然而，在其他实施例中，矩形通孔接触件的长度和宽度可以不同。 本发明的一些实施例提供具有非矩形端部的互连线。 在一些实施例中，互连线端部是部分八边形，六边形和/或圆形。 而且，一些实施例提供了不是矩形的Steiner点。 在一些实施例中，Steiner点是八边形，六边形或圆形。

    Simulating diagonal wiring directions using Manhattan directional wires
    14.
    发明授权
    Simulating diagonal wiring directions using Manhattan directional wires 有权
    使用曼哈顿方向导线模拟对角线路线方向

    公开(公告)号：US06900540B1

    公开(公告)日：2005-05-31

    申请号：US10043853

    申请日：2002-01-11

    申请人： Steven Teig ,  David Overhauser ,  Akira Fujimura

    发明人： Steven Teig ,  David Overhauser ,  Akira Fujimura

    IPC分类号： H01L23/528 ,  H01L23/48 ,  G06F17/50 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/528 ,  H01L2924/0002 ,  Y10T29/49162 ,  H01L2924/00

    摘要： An integrated circuit has a metal layer that includes conductors to provide interconnectivity for components of the integrated circuit chip. The metal layer is divided into at least two sections, such that a first section has a preferred direction and the second section has a preferred wiring direction that is different from the first preferred direction. The first and second preferred directions on a single metal layer may consist of any direction. The metal layer may be divided into more than two sections, wherein each section has a preferred wiring direction. Wiring geometries for multi-level metal layers are also disclosed.

    摘要翻译： 集成电路具有包括为集成电路芯片的组件提供互连的导体的金属层。 金属层被分成至少两个部分，使得第一部分具有优选的方向，并且第二部分具有不同于第一优选方向的优选的布线方向。 单个金属层上的第一和第二优选方向可由任何方向组成。 金属层可以被分成多于两个部分，其中每个部分具有优选的布线方向。 还公开了多层金属层的接线几何形状。

    Simulating euclidean wiring directions using manhattan and diagonal directional wires
    15.
    发明授权
    Simulating euclidean wiring directions using manhattan and diagonal directional wires 有权
    使用曼哈顿和对角方向线模拟欧几里德线路方向

    公开(公告)号：US06858935B1

    公开(公告)日：2005-02-22

    申请号：US10043808

    申请日：2002-01-11

    申请人： Steven Teig ,  David Overhauser ,  Akira Fujimura

    发明人： Steven Teig ,  David Overhauser ,  Akira Fujimura

    IPC分类号： H01L23/528 ,  H01L23/48

    CPC分类号： H01L23/528 ,  H01L2924/0002 ,  Y10T29/49162 ,  H01L2924/00

    摘要： An integrated circuit has a metal layer that includes conductors to provide interconnectivity for components of the integrated circuit chip. The metal layer is divided into at least two sections, such that a first section has a preferred direction and the second section has a preferred wiring direction that is different from the first preferred direction. The first and second preferred directions on a single metal layer may consist of any direction. The metal layer may be divided into more than two sections, wherein each section has a preferred wiring direction. Wiring geometries for multi-level metal layers are also disclosed.

    摘要翻译： 集成电路具有包括为集成电路芯片的组件提供互连的导体的金属层。 金属层被分成至少两个部分，使得第一部分具有优选的方向，并且第二部分具有不同于第一优选方向的优选的布线方向。 单个金属层上的第一和第二优选方向可由任何方向组成。 金属层可以被分成多于两个部分，其中每个部分具有优选的布线方向。 还公开了多层金属层的接线几何形状。

    Method and system for distributing clock signals on non manhattan semiconductor integrated circuits
    16.
    发明授权
    Method and system for distributing clock signals on non manhattan semiconductor integrated circuits 失效
    在非曼哈顿半导体集成电路上分配时钟信号的方法和系统

    公开(公告)号：US08671378B2

    公开(公告)日：2014-03-11

    申请号：US12772967

    申请日：2010-05-03

    申请人： Steven Teig ,  Raghu Chalasani ,  Akira Fujimura

    发明人： Steven Teig ,  Raghu Chalasani ,  Akira Fujimura

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  G06F1/10 ,  G06F2217/62

    摘要： The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal structure is rendered after transforming the coordinates system such that a rotated recursive H clock signal structure is rendered. In another embodiment, a recursive Y structure is used to create a clock signal structure. The recursive Y structure may also be implemented in a rotated alignment. For clock signal redundancy, non Manhattan wiring may be used to create a clock signal mesh network.

    摘要翻译： 本发明介绍了用于在集成电路布局中路由时钟信号的方法，系统和架构。 引入的时钟信号时钟信号结构以非曼哈顿路由呈现。 在第一实施例中，传统的递归H时钟信号结构在变换坐标系之后呈现，从而呈现旋转的递归H时钟信号结构。 在另一个实施例中，使用递归Y结构来创建时钟信号结构。 递归Y结构也可以以旋转的对准来实现。 对于时钟信号冗余，可以使用非曼哈顿布线来创建时钟信号网状网络。

    Method and system for distributing clock signals on non manhattan semiconductor integrated circuit using parameterized rotation
    17.
    发明授权
    Method and system for distributing clock signals on non manhattan semiconductor integrated circuit using parameterized rotation 失效
    使用参数化旋转在非曼哈顿半导体集成电路上分配时钟信号的方法和系统

    公开(公告)号：US07730441B2

    公开(公告)日：2010-06-01

    申请号：US11548655

    申请日：2006-10-11

    申请人： Steven Teig ,  Raghu Chalasani ,  Akira Fujimura

    发明人： Steven Teig ,  Raghu Chalasani ,  Akira Fujimura

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  G06F1/10 ,  G06F2217/62

    摘要： The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal structure is rendered after transforming the coordinates system such that a rotated recursive H clock signal structure is rendered. In another embodiment, a recursive Y structure is used to create a clock signal structure. The recursive Y structure may also be implemented in a rotated alignment. For clock signal redundancy, non Manhattan wiring may be used to create a clock signal mesh network.

    摘要翻译： 本发明介绍了用于在集成电路布局中路由时钟信号的方法，系统和架构。 引入的时钟信号时钟信号结构以非曼哈顿路由呈现。 在第一实施例中，传统的递归H时钟信号结构在变换坐标系之后呈现，从而呈现旋转的递归H时钟信号结构。 在另一个实施例中，使用递归Y结构来创建时钟信号结构。 递归Y结构也可以以旋转的对准来实现。 对于时钟信号冗余，可以使用非曼哈顿布线来创建时钟信号网状网络。

    Integrated circuit diagonal wiring architectures with zag conductors
    18.
    发明授权
    Integrated circuit diagonal wiring architectures with zag conductors 有权
    集成电路对角布线结构，带有扎扎导体

    公开(公告)号：US06858939B1

    公开(公告)日：2005-02-22

    申请号：US09681776

    申请日：2001-06-03

    申请人： Steven Teig ,  David Overhauser ,  Akira Fujimura

    发明人： Steven Teig ,  David Overhauser ,  Akira Fujimura

    IPC分类号： H01L23/528 ,  H01I23/48

    CPC分类号： H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit has a metal layer that includes conductors to provide interconnectivity for components of the integrated circuit chip. The metal layer is divided into at least two sections, such that a first section has a preferred direction and the second section has a preferred wiring direction that is different from the first preferred direction. The first and second preferred directions on a single metal layer may consist of any direction. The metal layer may be divided into more than two sections, wherein each section has a preferred wiring direction. Wiring geometries for multi-level metal layers are also disclosed.

    摘要翻译： 集成电路具有包括为集成电路芯片的组件提供互连的导体的金属层。 金属层被分成至少两个部分，使得第一部分具有优选的方向，并且第二部分具有不同于第一优选方向的优选的布线方向。 单个金属层上的第一和第二优选方向可由任何方向组成。 金属层可以被分成多于两个部分，其中每个部分具有优选的布线方向。 还公开了多层金属层的接线几何形状。