利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

37 条记录 (耗时 0.056 秒)

    Nonvolatile semiconductor memory device
    11.
    发明申请
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US20050095769A1

    公开(公告)日：2005-05-05

    申请号：US10499667

    申请日：2002-02-28

    申请人： Yoshinori Takase ,  Hideaki Kurata ,  Keiichi Yoshida ,  Ken Matsubara ,  Michitaro Kanamitsu ,  Shinji Yuasa

    发明人： Yoshinori Takase ,  Hideaki Kurata ,  Keiichi Yoshida ,  Ken Matsubara ,  Michitaro Kanamitsu ,  Shinji Yuasa

    IPC分类号： G11C16/04 ,  G11C16/24 ,  G11C16/34 ,  H01L21/8238

    CPC分类号： G11C16/16 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2216/18

    摘要： A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order. The method realizes, particularly, (1) suppression of the number of erase verification times to the minimum by performing erase verification only on arbitrary one even-numbered or odd-numbered page in the pages to be erased in consideration of variations in the erasing characteristic, and (2) prevention of erroneous determination of the upper end of erasure since it is unnecessary to set a memory cell to be rewritten every rewrite verification by continuously executing the rewriting process page by page.

    摘要翻译： 一种非易失性半导体存储器件，其能够在存储器阵列配置中实现优化的擦除操作，其中多个页面对应于并连接到多个字线中的每一个并且更高的擦除操作速度。 在闪速存储器中，通过擦除多个任意选择的多个页面的擦除方法进行擦除操作。 在两页擦除模式中，按顺序执行页擦除，页预擦除验证，页重写处理，页预重写验证和页上限确定处理。 该方法特别地实现（1）通过仅在擦除页面中的任意一个偶数页或奇数页上执行擦除验证，以便考虑到擦除特性的变化来将擦除验证次数抑制到最小 ，以及（2）防止擦除上端的错误判断，因为不必每次重写验证来设置要重写的存储单元，通过逐页连续执行重写处理。

    Nonvolatile semiconductor memory device
    12.
    发明申请
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US20050105373A1

    公开(公告)日：2005-05-19

    申请号：US10505952

    申请日：2002-02-28

    申请人： Yoshinori Takase ,  Hideaki Kurata ,  Keiichi Yoshida ,  Michitaro Kanamitsu

    发明人： Yoshinori Takase ,  Hideaki Kurata ,  Keiichi Yoshida ,  Michitaro Kanamitsu

    IPC分类号： G11C11/00 ,  G11C11/56 ,  G11C16/24 ,  G11C16/26 ,  G11C8/02

    CPC分类号： G11C16/26 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/24

    摘要： This is a nonvolatile semiconductor memory device capable of raising the speed of write operation of Y access circuits in a 1×sense latch circuit+2×SRAM configuration. In a multi-value flash memory, in a mode of writing from the lower voltage side, writing and erratic determination are performed after data are transferred from SRAMs to a sense latch circuit for “10” and “00” distributions; after the data transfer for “01” distribution, writing is done; after the data transfer for “11” distribution word disturb determination is done; and simplified upper limit determination is done in this sequence. In particular by (1) writing from the lower voltage side of the threshold voltage distribution in the multi-value memory and (2) consecutive application of “write processing” and “upper limit determination processing” to each threshold voltage distribution, after the end of write processing for “10” and “00” distribution, since the threshold voltages of all the memory cells are lower than the upper limit determination voltages of the “10” and “00” distributions, no transfer of write data is needed in upper limit determination processing because other threshold voltage distributions are not masked.

    摘要翻译： 这是一种非易失性半导体存储器件，其能够以1倍锁存电路+ 2xSRAM配置提高Y个存取电路的写入操作速度。 在多值闪速存储器中，在从低电压侧进行写入的情况下，在数据从SRAM向“10”，“00”分布的感测锁存电路进行数据的写入和不稳定判定之后， 在“01”分发数据传输之后，写入完成; 在数据传输“11”分配字干扰确定完成后; 并且在该顺序中进行简化的上限确定。 特别是通过（1）从多值存储器中的阈值电压分布的低电压侧写入，以及（2）在每个阈值电压分布之后连续施加“写入处理”和“上限确定处理” 对于“10”和“00”分配的写入处理，由于所有存储单元的阈值电压都低于“10”和“00”分布的上限确定电压，所以上层不需要写入数据传输 因为其他阈值电压分布未被屏蔽，所以限制确定处理。

    Nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array
    13.
    发明授权
    Nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array 有权
    能够在存储器阵列中实现优化的擦除操作的非易失性半导体存储器件

    公开(公告)号：US07095657B2

    公开(公告)日：2006-08-22

    申请号：US11224964

    申请日：2005-09-14

    申请人： Yoshinori Takase ,  Hideaki Kurata ,  Keiichi Yoshida ,  Ken Matsubara ,  Michitaro Kanamitsu ,  Shinji Yuasa

    发明人： Yoshinori Takase ,  Hideaki Kurata ,  Keiichi Yoshida ,  Ken Matsubara ,  Michitaro Kanamitsu ,  Shinji Yuasa

    IPC分类号： G11C7/10

    CPC分类号： G11C16/16 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2216/18

    摘要： A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order. The method realizes, particularly, (1) suppression of the number of erase verification times to the minimum by performing erase verification only on arbitrary one even-numbered or odd-numbered page in the pages to be erased in consideration of variations in the erasing characteristic, and (2) prevention of erroneous determination of the upper end of erasure since it is unnecessary to set a memory cell to be rewritten every rewrite verification by continuously executing the rewriting process page by page.

    摘要翻译： 一种非易失性半导体存储器件，其能够在存储器阵列配置中实现优化的擦除操作，其中多个页面对应于并连接到多个字线中的每一个并且更高的擦除操作速度。 在闪速存储器中，通过擦除多个任意选择的多个页面的擦除方法进行擦除操作。 在两页擦除模式中，按顺序执行页擦除，页预擦除验证，页重写处理，页预重写验证和页上限确定处理。 该方法特别地实现（1）通过仅在擦除页面中的任意一个偶数页或奇数页上执行擦除验证，以便考虑到擦除特性的变化来将擦除验证次数抑制到最小 ，以及（2）防止擦除上端的错误判断，因为不必每次重写验证来设置要重写的存储单元，通过逐页连续执行重写处理。

    Nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array
    14.
    发明授权
    Nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array 有权
    能够在存储器阵列中实现优化的擦除操作的非易失性半导体存储器件

    公开(公告)号：US06958940B2

    公开(公告)日：2005-10-25

    申请号：US10499667

    申请日：2002-02-28

    申请人： Yoshinori Takase ,  Hideaki Kurata ,  Keiichi Yoshida ,  Ken Matsubara ,  Michitaro Kanamitsu ,  Shinji Yuasa

    发明人： Yoshinori Takase ,  Hideaki Kurata ,  Keiichi Yoshida ,  Ken Matsubara ,  Michitaro Kanamitsu ,  Shinji Yuasa

    IPC分类号： G11C16/04 ,  G11C16/24 ,  G11C16/34

    CPC分类号： G11C16/16 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2216/18

    摘要： A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order. The method realizes, particularly, (1) suppression of the number of erase verification times to the minimum by performing erase verification only on arbitrary one even-numbered or odd-numbered page in the pages to be erased in consideration of variations in the erasing characteristic, and (2) prevention of erroneous determination of the upper end of erasure since it is unnecessary to set a memory cell to be rewritten every rewrite verification by continuously executing the rewriting process page by page.

    摘要翻译： 一种非易失性半导体存储器件，其能够在存储器阵列配置中实现优化的擦除操作，其中多个页面对应于并连接到多个字线中的每一个并且更高的擦除操作速度。 在闪速存储器中，通过擦除多个任意选择的多个页面的擦除方法进行擦除操作。 在两页擦除模式中，按顺序执行页擦除，页预擦除验证，页重写处理，页预重写验证和页上限确定处理。 该方法特别地实现（1）通过仅在擦除页面中的任意一个偶数页或奇数页上执行擦除验证，以便考虑到擦除特性的变化来将擦除验证次数抑制到最小 ，以及（2）防止擦除上端的错误判断，因为不必每次重写验证来设置要重写的存储单元，通过逐页连续执行重写处理。

    Nonvolatile semiconductor memory including a controller for providing an improved reprogram operation
    17.
    发明授权
    Nonvolatile semiconductor memory including a controller for providing an improved reprogram operation 有权
    非易失性半导体存储器包括用于提供改进的重新编程操作的控制器

    公开(公告)号：US06333871B1

    公开(公告)日：2001-12-25

    申请号：US09539634

    申请日：2000-03-30

    申请人： Tetsuya Tsujikawa ,  Atsushi Nozoe ,  Michitaro Kanamitsu ,  Shoji Kubono ,  Eiji Yamamoto ,  Ken Matsubara

    发明人： Tetsuya Tsujikawa ,  Atsushi Nozoe ,  Michitaro Kanamitsu ,  Shoji Kubono ,  Eiji Yamamoto ,  Ken Matsubara

    IPC分类号： G11C1604

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3463 ,  G11C2211/5642

    摘要： Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.

    摘要翻译： 外部提供的程序数据被锁存到数据锁存电路DLL和DLR中。 在执行多个编程操作的每一次时，判定所锁存的程序数据是否对应于多级的任何阈值。 与判断结果相对应的程序控制信息被锁存在读出锁存电路SL中。 基于锁存的程序控制信息，以逐步的方式执行用于将具有多级的阈值电压设置到存储器单元的编程操作。 即使编程操作结束，外部提供的程序数据也留在数据锁存电路中。 即使由于过度编程条件而重试存储器单元的编程操作，也不再需要再次从外部设备接收程序数据。

    Non-volatile memory system including a control device to control writing, reading and storage and output operations of non-volatile devices including memory cells and data latches
    19.
    发明授权
    Non-volatile memory system including a control device to control writing, reading and storage and output operations of non-volatile devices including memory cells and data latches 有权
    非易失性存储器系统，包括用于控制包括存储器单元和数据锁存器的非易失性器件的写入，读取和存储和输出操作的控制装置

    公开(公告)号：US06721207B2

    公开(公告)日：2004-04-13

    申请号：US10211342

    申请日：2002-08-05

    申请人： Tetsuya Tsujikawa ,  Atsushi Nozoe ,  Michitaro Kanamitsu ,  Shoji Kubono ,  Eiji Yamamoto ,  Ken Matsubara

    发明人： Tetsuya Tsujikawa ,  Atsushi Nozoe ,  Michitaro Kanamitsu ,  Shoji Kubono ,  Eiji Yamamoto ,  Ken Matsubara

    IPC分类号： G51C1604

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3463 ,  G11C2211/5642

    摘要： A non-volatile memory system is provided with a control device and non-volatile memory devices, each including memory cells and data latches. The control device supplies commands to the non-volatile memory devices, including a write command, and first and second read commands. When the control device supplies the write command with write address information and data for storing in the non-volatile memory device, it stores the data to the data latches and then to the memory cells, and then verifies storage. When the control device supplies the first read command with read address information, the nonvolatile memory device reads data stored in the memory cells to the data latches and then outputs the data in the data latches to the control device. When the control device supplies the second read command, the non-volatile memory device outputs data in the data latches to the control device.

    摘要翻译： 非易失性存储器系统设置有控制设备和非易失性存储器设备，每个包括存储器单元和数据锁存器。 控制装置向非易失性存储装置提供包括写入命令以及第一和第二读取命令的命令。 当控制装置向写入命令提供写入地址信息和用于存储在非易失性存储器件中的数据时，它将数据存储到数据锁存器，然后存储到存储器单元，然后验证存储器。 当控制装置向读取地址信息提供第一读取命令时，非易失性存储器件将存储在存储器单元中的数据读取到数据锁存器，然后将数据锁存器中的数据输出到控制装置。 当控制装置提供第二读取命令时，非易失性存储装置将数据锁存器中的数据输出到控制装置。

    Nonvolatile memory system
    20.
    发明授权
    Nonvolatile memory system 有权
    非易失性存储器系统

    公开(公告)号：US06507520B2

    公开(公告)日：2003-01-14

    申请号：US10011723

    申请日：2001-12-11

    申请人： Tetsuya Tsujikawa ,  Atsushi Nozoe ,  Michitaro Kanamitsu ,  Shoji Kubono ,  Eiji Yamamoto ,  Ken Matsubara

    发明人： Tetsuya Tsujikawa ,  Atsushi Nozoe ,  Michitaro Kanamitsu ,  Shoji Kubono ,  Eiji Yamamoto ,  Ken Matsubara

    IPC分类号： G11C1604

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3463 ,  G11C2211/5642

    摘要： Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.

    摘要翻译： 外部提供的程序数据被锁存在数据锁存电路DLL和DLR中。 在执行多个编程操作的每一次时，判定所锁存的程序数据是否对应于多级的任何阈值。 与判断结果相对应的程序控制信息被锁存在读出锁存电路SL中。 基于锁存的程序控制信息，以逐步的方式执行用于将具有多级的阈值电压设置到存储器单元的编程操作。 即使编程操作结束，外部提供的程序数据也留在数据锁存电路中。 即使由于过度编程条件而重试存储器单元的编程操作，也不再需要再次从外部设备接收程序数据。