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    Nonvolatile semiconductor memory device
    1.
    发明申请
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US20060007737A1

    公开(公告)日：2006-01-12

    申请号：US11224964

    申请日：2005-09-14

    申请人： Yoshinori Takase ,  Hideaki Kurata ,  Keiichi Yoshida ,  Ken Matsubara ,  Michitaro Kanamitsu ,  Shinji Yuasa

    发明人： Yoshinori Takase ,  Hideaki Kurata ,  Keiichi Yoshida ,  Ken Matsubara ,  Michitaro Kanamitsu ,  Shinji Yuasa

    IPC分类号： G11C11/34

    CPC分类号： G11C16/16 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2216/18

    摘要： A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order. The method realizes, particularly, (1) suppression of the number of erase verification times to the minimum by performing erase verification only on arbitrary one even-numbered or odd-numbered page in the pages to be erased in consideration of variations in the erasing characteristic, and (2) prevention of erroneous determination of the upper end of erasure since it is unnecessary to set a memory cell to be rewritten every rewrite verification by continuously executing the rewriting process page by page.

    摘要翻译： 一种非易失性半导体存储器件，其能够在存储器阵列配置中实现优化的擦除操作，其中多个页面对应于并连接到多个字线中的每一个并且更高的擦除操作速度。 在闪速存储器中，通过擦除多个任意选择的多个页面的擦除方法进行擦除操作。 在两页擦除模式中，按顺序执行页擦除，页预擦除验证，页重写处理，页预重写验证和页上限确定处理。 该方法特别地实现（1）通过仅在擦除页面中的任意一个偶数页或奇数页上执行擦除验证，以便考虑到擦除特性的变化来将擦除验证次数抑制到最小 ，以及（2）防止擦除上端的错误判断，因为不必每次重写验证来设置要重写的存储单元，通过逐页连续执行重写处理。

    Nonvolatile semiconductor memory device
    2.
    发明申请
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US20050095769A1

    公开(公告)日：2005-05-05

    申请号：US10499667

    申请日：2002-02-28

    申请人： Yoshinori Takase ,  Hideaki Kurata ,  Keiichi Yoshida ,  Ken Matsubara ,  Michitaro Kanamitsu ,  Shinji Yuasa

    发明人： Yoshinori Takase ,  Hideaki Kurata ,  Keiichi Yoshida ,  Ken Matsubara ,  Michitaro Kanamitsu ,  Shinji Yuasa

    IPC分类号： G11C16/04 ,  G11C16/24 ,  G11C16/34 ,  H01L21/8238

    CPC分类号： G11C16/16 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2216/18

    摘要： A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order. The method realizes, particularly, (1) suppression of the number of erase verification times to the minimum by performing erase verification only on arbitrary one even-numbered or odd-numbered page in the pages to be erased in consideration of variations in the erasing characteristic, and (2) prevention of erroneous determination of the upper end of erasure since it is unnecessary to set a memory cell to be rewritten every rewrite verification by continuously executing the rewriting process page by page.

    摘要翻译： 一种非易失性半导体存储器件，其能够在存储器阵列配置中实现优化的擦除操作，其中多个页面对应于并连接到多个字线中的每一个并且更高的擦除操作速度。 在闪速存储器中，通过擦除多个任意选择的多个页面的擦除方法进行擦除操作。 在两页擦除模式中，按顺序执行页擦除，页预擦除验证，页重写处理，页预重写验证和页上限确定处理。 该方法特别地实现（1）通过仅在擦除页面中的任意一个偶数页或奇数页上执行擦除验证，以便考虑到擦除特性的变化来将擦除验证次数抑制到最小 ，以及（2）防止擦除上端的错误判断，因为不必每次重写验证来设置要重写的存储单元，通过逐页连续执行重写处理。

    Nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array
    3.
    发明授权
    Nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array 有权
    能够在存储器阵列中实现优化的擦除操作的非易失性半导体存储器件

    公开(公告)号：US07095657B2

    公开(公告)日：2006-08-22

    申请号：US11224964

    申请日：2005-09-14

    申请人： Yoshinori Takase ,  Hideaki Kurata ,  Keiichi Yoshida ,  Ken Matsubara ,  Michitaro Kanamitsu ,  Shinji Yuasa

    发明人： Yoshinori Takase ,  Hideaki Kurata ,  Keiichi Yoshida ,  Ken Matsubara ,  Michitaro Kanamitsu ,  Shinji Yuasa

    IPC分类号： G11C7/10

    CPC分类号： G11C16/16 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2216/18

    摘要： A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order. The method realizes, particularly, (1) suppression of the number of erase verification times to the minimum by performing erase verification only on arbitrary one even-numbered or odd-numbered page in the pages to be erased in consideration of variations in the erasing characteristic, and (2) prevention of erroneous determination of the upper end of erasure since it is unnecessary to set a memory cell to be rewritten every rewrite verification by continuously executing the rewriting process page by page.

    摘要翻译： 一种非易失性半导体存储器件，其能够在存储器阵列配置中实现优化的擦除操作，其中多个页面对应于并连接到多个字线中的每一个并且更高的擦除操作速度。 在闪速存储器中，通过擦除多个任意选择的多个页面的擦除方法进行擦除操作。 在两页擦除模式中，按顺序执行页擦除，页预擦除验证，页重写处理，页预重写验证和页上限确定处理。 该方法特别地实现（1）通过仅在擦除页面中的任意一个偶数页或奇数页上执行擦除验证，以便考虑到擦除特性的变化来将擦除验证次数抑制到最小 ，以及（2）防止擦除上端的错误判断，因为不必每次重写验证来设置要重写的存储单元，通过逐页连续执行重写处理。

    Nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array
    4.
    发明授权
    Nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array 有权
    能够在存储器阵列中实现优化的擦除操作的非易失性半导体存储器件

    公开(公告)号：US06958940B2

    公开(公告)日：2005-10-25

    申请号：US10499667

    申请日：2002-02-28

    申请人： Yoshinori Takase ,  Hideaki Kurata ,  Keiichi Yoshida ,  Ken Matsubara ,  Michitaro Kanamitsu ,  Shinji Yuasa

    发明人： Yoshinori Takase ,  Hideaki Kurata ,  Keiichi Yoshida ,  Ken Matsubara ,  Michitaro Kanamitsu ,  Shinji Yuasa

    IPC分类号： G11C16/04 ,  G11C16/24 ,  G11C16/34

    CPC分类号： G11C16/16 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2216/18

    摘要： A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order. The method realizes, particularly, (1) suppression of the number of erase verification times to the minimum by performing erase verification only on arbitrary one even-numbered or odd-numbered page in the pages to be erased in consideration of variations in the erasing characteristic, and (2) prevention of erroneous determination of the upper end of erasure since it is unnecessary to set a memory cell to be rewritten every rewrite verification by continuously executing the rewriting process page by page.

    摘要翻译： 一种非易失性半导体存储器件，其能够在存储器阵列配置中实现优化的擦除操作，其中多个页面对应于并连接到多个字线中的每一个并且更高的擦除操作速度。 在闪速存储器中，通过擦除多个任意选择的多个页面的擦除方法进行擦除操作。 在两页擦除模式中，按顺序执行页擦除，页预擦除验证，页重写处理，页预重写验证和页上限确定处理。 该方法特别地实现（1）通过仅在擦除页面中的任意一个偶数页或奇数页上执行擦除验证，以便考虑到擦除特性的变化来将擦除验证次数抑制到最小 ，以及（2）防止擦除上端的错误判断，因为不必每次重写验证来设置要重写的存储单元，通过逐页连续执行重写处理。

    Nonvolatile memory and method of programming the same memory
    5.
    发明授权
    Nonvolatile memory and method of programming the same memory 有权

    公开(公告)号：US06567315B2

    公开(公告)日：2003-05-20

    申请号：US10012549

    申请日：2001-12-12

    申请人： Yoshinori Takase ,  Shoji Kubono ,  Michitaro Kanamitsu ,  Atsushi Nozoe ,  Keiichi Yoshida ,  Hideaki Kurata

    发明人： Yoshinori Takase ,  Shoji Kubono ,  Michitaro Kanamitsu ,  Atsushi Nozoe ,  Keiichi Yoshida ,  Hideaki Kurata

    IPC分类号： G11C1604

    CPC分类号： G11C16/3459 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/12

    摘要： There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases. In the non-volatile memory of the invention comprising the AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, the local drain lines are precharged by supplying thereto a comparatively higher voltage from the common drain line side (opposite side of the main bit lines), the main bit lines are selectively precharged by applying thereto the voltage of 0V or a comparatively small voltage depending on the write data and thereafter a drain current is applied only to the selected memory cells to which data is written by applying the write voltage to the word lines in order to implant the hot electrons to the floating gate.

    Nonvolatile memory and method of programming the same memory
    6.
    发明授权
    Nonvolatile memory and method of programming the same memory 有权
    非易失性存储器和编程相同存储器的方法

    公开(公告)号：US06930924B2

    公开(公告)日：2005-08-16

    申请号：US10404101

    申请日：2003-04-02

    申请人： Yoshinori Takase ,  Shoji Kubono ,  Michitaro Kanamitsu ,  Atsushi Nozoe ,  Keiichi Yoshida ,  Hideaki Kurata

    发明人： Yoshinori Takase ,  Shoji Kubono ,  Michitaro Kanamitsu ,  Atsushi Nozoe ,  Keiichi Yoshida ,  Hideaki Kurata

    IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12

    CPC分类号： G11C16/3459 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/12

    摘要： There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases. In the non-volatile memory of the invention comprising the AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, the local drain lines are precharged by supplying thereto a comparatively higher voltage from the common drain line side (opposite side of the main bit lines), the main bit lines are selectively precharged by applying thereto the voltage of 0V or a comparatively small voltage depending on the write data and thereafter a drain current is applied only to the selected memory cells to which data is written by applying the write voltage to the word lines in order to implant the hot electrons to the floating gate.

    摘要翻译： 提供了一种编程非易失性存储器的方法，其可以解决现有闪存的数据写入系统的问题，即位线的负载电容变大，位线达到预定电位所需的时间变为 因此，数据写入操作所需的时间变得更长，并且由于存储器阵列的存储器电容越多，存储器阵列的长度越长，位线的数量越多，位线的数量越多，因此功耗也变大。 在本发明的非易失性存储器中，包括其中多个存储器单元并联连接在局部位线和局部漏极线之间的AND型存储器阵列，通过向局部漏极线提供相对较高的电压来预充电， 公共漏极线侧（主位线的相对侧），主位线通过向其施加0V的电压或根据写入数据的相对较小的电压来选择性地预充电，此后，漏极电流仅施加到所选择的 通过将写入电压施加到字线来写入数据的存储器单元，以便将热电子注入浮动栅极。

    Nonvolatile semiconductor memory device
    7.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US07002848B2

    公开(公告)日：2006-02-21

    申请号：US10505952

    申请日：2002-02-28

    申请人： Yoshinori Takase ,  Hideaki Kurata ,  Keiichi Yoshida ,  Michitaro Kanamitsu

    发明人： Yoshinori Takase ,  Hideaki Kurata ,  Keiichi Yoshida ,  Michitaro Kanamitsu

    IPC分类号： G11C16/04

    CPC分类号： G11C16/26 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/24

    摘要： This is a nonvolatile semiconductor memory device capable of raising the speed of write operation of Y access circuits in a 1×sense latch circuit+2×SRAM configuration. In a multi-value flash memory, in a mode of writing from the lower voltage side, writing and erratic determination are performed after data are transferred from SRAMs to a sense latch circuit for “10” and “00” distributions; after the data transfer for “01” distribution, writing is done; after the data transfer for “11” distribution word disturb determination is done; and simplified upper limit determination is done in this sequence. In particular by (1) writing from the lower voltage side of the threshold voltage distribution in the multi-value memory and (2) consecutive application of “write processing” and “upper limit determination processing” to each threshold voltage distribution, after the end of write processing for “10” and “00” distribution, since the threshold voltages of all the memory cells are lower than the upper limit determination voltages of the “10” and “00” distributions, no transfer of write data is needed in upper limit determination processing because other threshold voltage distributions are not masked.

    摘要翻译： 这是一种非易失性半导体存储器件，其能够以1倍锁存电路+ 2xSRAM配置提高Y个存取电路的写入操作速度。 在多值闪速存储器中，在从低电压侧进行写入的情况下，在数据从SRAM向“10”，“00”分布的感测锁存电路进行数据的写入和不稳定判定之后， 在“01”分发数据传输之后，写入完成; 在数据传输“11”分配字干扰确定完成后; 并且在该顺序中进行简化的上限确定。 特别是通过（1）从多值存储器中的阈值电压分布的低电压侧写入，以及（2）在每个阈值电压分布之后连续施加“写入处理”和“上限确定处理” 对于“10”和“00”分配的写入处理，由于所有存储单元的阈值电压都低于“10”和“00”分布的上限确定电压，所以上层不需要写入数据传输 因为其他阈值电压分布未被屏蔽，所以限制确定处理。

    Nonvolatile memory and method of programming the same memory
    8.
    发明申请
    Nonvolatile memory and method of programming the same memory 失效

    公开(公告)号：US20050237803A1

    公开(公告)日：2005-10-27

    申请号：US11168331

    申请日：2005-06-29

    申请人： Yoshinori Takase ,  Shoji Kubono ,  Michitaro Kanamitsu ,  Atsushi Nozoe ,  Keiichi Yoshida ,  Hideaki Kurata

    发明人： Yoshinori Takase ,  Shoji Kubono ,  Michitaro Kanamitsu ,  Atsushi Nozoe ,  Keiichi Yoshida ,  Hideaki Kurata

    IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12

    CPC分类号： G11C16/3459 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/12

    摘要： There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases. In the non-volatile memory of the invention comprising the AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, the local drain lines are precharged by supplying thereto a comparatively higher voltage from the common drain line side (opposite side of the main bit lines), the main bit lines are selectively precharged by applying thereto the voltage of 0V or a comparatively small voltage depending on the write data and thereafter a drain current is applied only to the selected memory cells to which data is written by applying the write voltage to the word lines in order to implant the hot electrons to the floating gate.