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115 条记录 (耗时 0.03 秒)

    Flat display
    15.
    发明授权
    Flat display 失效
    平面显示

    公开(公告)号：US6023258A

    公开(公告)日：2000-02-08

    申请号：US624054

    申请日：1996-03-29

    申请人： Hirohito Kuriyama ,  Toshio Ueda ,  Keiichi Kaneko ,  Akira Yamamoto

    发明人： Hirohito Kuriyama ,  Toshio Ueda ,  Keiichi Kaneko ,  Akira Yamamoto

    IPC分类号： H04N5/66 ,  G09G3/20 ,  G09G3/288 ,  G09G3/291 ,  G09G3/292 ,  G09G3/294 ,  G09G3/296 ,  G09G3/298 ,  H04N5/70 ,  H04N9/20 ,  G09G3/28

    CPC分类号： G09G3/2927 ,  G09G3/2944 ,  G09G3/2946 ,  G09G2310/066 ,  G09G2320/0606 ,  G09G2320/0626 ,  G09G2330/021

    摘要： The present invention provides a flat display including a high-speed arithmetic logic facility so that, even when a data signal for a first line follows immediately after a frame start signal, the display displays an image with stable display quality quickly. For controlling driving signals in a flat display, each sub-frame of a temporally-segmented frame comprises at least an initialization period S1' during which a display screen is initialized, an addressing period S2 during which a plurality of cells are selected and written with display data, and a sustaining discharge period S3 during which the cells which contain display data are discharged so as to emit light for a given period of time. The flat display includes an initialization start time control unit 100 that detects the input of a display start signal V.sub.SYNC for one frame, and controls an initialization start time ST of the initialization period S1' so that the ST will precede an instant of input of a frame start signal V.sub.SYNC.

    摘要翻译： 本发明提供了一种包括高速算术逻辑设备的平面显示器，使得即使在帧起始信号之后紧接着第一行的数据信号，显示器就快速显示具有稳定的显示质量的图像。 为了控制平面显示器中的驱动信号，时间分段帧的每个子帧至少包括一个初始化周期S1'，在该初始化周期S1'期间初始化显示画面，寻址周期S2期间多个单元被选择并写入 显示数据和包含显示数据的单元被放电以在给定时间段内发光的维持放电周期S3。 平面显示器包括初始化开始时间控制单元100，其检测一帧的显示开始信号VSYNC的输入，并且控制初始化时段S1'的初始化开始时间ST，使得ST将在输入的时刻之前 帧起始信号VSYNC。

    Error diffusion processing circuit and method, and plasma display device
    16.
    发明申请
    Error diffusion processing circuit and method, and plasma display device 审中-公开
    误差扩散处理电路及方法及等离子体显示装置

    公开(公告)号：US20070230813A1

    公开(公告)日：2007-10-04

    申请号：US11358740

    申请日：2006-02-22

    申请人： Akira Yamamoto ,  Masaya Tajima ,  Toshio Ueda

    发明人： Akira Yamamoto ,  Masaya Tajima ,  Toshio Ueda

    IPC分类号： G06K9/36

    CPC分类号： G09G3/2066 ,  G09G3/298 ,  G09G2310/0232 ,  G09G2320/0673

    摘要： An error diffusion processing circuit is provided which has a separator dividing digital pixel data of an object pixel into high bits and low bits, and making the low bits error data, multiplier circuits multiplying transmission error data of a plurality of adjacent pixels by adjacent pixel weighting coefficients, and outputting weighted transmission error data, a first adder circuit performing addition on the basis of the error data of the object pixel, and the weighted transmission error data of adjacent pixels, and outputting an added value and a carry value, a second adder circuit adding the high bit pixel data of the object pixel and the carry value, and outputting output pixel data, and a correction circuit correcting transmission error data of an adjacent pixel to the error data of the object pixel or data obtained by performing arithmetic processing of it when the transmission error data of the adjacent pixel is 0, and outputting it to the corresponding multiplier circuit.

    摘要翻译： 提供了一种误差扩散处理电路，其具有将目标像素的数字像素数据分割为高位和低位的分离器，并且使低位误差数据乘法器电路将多个相邻像素的传输误差数据相乘，通过相邻像素加权 系数，并且输出加权的传输错误数据;第一加法器电路，基于对象像素的误差数据和相邻像素的加权传输错误数据执行相加，并输出相加值和进位值;第二加法器 将目标像素的高位像素数据和进位值相加，并输出输出像素数据，以及校正电路，将相邻像素的传输误差数据修正为对象像素的误差数据或通过进行运算处理获得的数据 当相邻像素的传输错误数据为0时，将其输出到相应的乘法器电路。