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12 条记录 (耗时 0.03 秒)

    Method and device for decoding moving picture
    9.
    发明授权
    Method and device for decoding moving picture 有权
    解码运动图像的方法和装置

    公开(公告)号：US06658154B2

    公开(公告)日：2003-12-02

    申请号：US09365865

    申请日：1999-08-03

    申请人： Kiyoshi Kohiyama ,  Yukio Otobe ,  Hidenaga Takahashi ,  Koji Yoshitomi

    发明人： Kiyoshi Kohiyama ,  Yukio Otobe ,  Hidenaga Takahashi ,  Koji Yoshitomi

    IPC分类号： G06K946

    CPC分类号： G06T1/60 ,  H04N19/176 ,  H04N19/423 ,  H04N19/61 ,  H04N19/90

    摘要： A memory control part 12 cyclically assigns time slots to buffer memory parts 21 to 25 respectively and in each time slot, controls access between the corresponding buffer memory part and a synchronous RAM 11. A time slot is determined while assuming the worst case where access to the synchronous RAM is the severest. Time slot groups of [(the number of pixels on one horizontal scanning line)/256] in number are generated in an imaginary one horizontal scanning period, where [ ] denotes an integer portion of the number in the parentheses. For a buffer memory 22 whose data volume changes depending on a compression factor, a time slot ending point may be made variable, or a time slot may be generated by interrupt as an exception.

    摘要翻译： 存储器控制部分12分别循环地将时隙分配给缓冲存储器部分21至25，并且在每个时隙中控制对应的缓冲存储器部分和同步RAM 11之间的访问。确定时隙，同时假定访问 同步RAM是最严重的。 数字中的[（一条水平扫描线上的像素数）/ 256]的时隙组在虚拟的一个水平扫描周期中生成，其中[]表示括号中的数字的整数部分。 对于其数据量根据压缩因子而变化的缓冲存储器22，可以使时隙终点可变，或者可以通过中断产生时隙作为例外。

    One-chip first-in first-out memory device having matched write and read operations
    10.
    发明授权
    One-chip first-in first-out memory device having matched write and read operations 失效
    具有匹配的写入和读取操作的单芯片先进先出的存储器件

    公开(公告)号：US5220529A

    公开(公告)日：1993-06-15

    申请号：US747047

    申请日：1991-08-19

    申请人： Kiyoshi Kohiyama ,  Hidenaga Takahashi ,  Yukio Otobe

    发明人： Kiyoshi Kohiyama ,  Hidenaga Takahashi ,  Yukio Otobe

    IPC分类号： G06F5/10 ,  G11C8/04

    CPC分类号： G06F5/10 ,  G11C8/04

    摘要： A write operation is performed by using a sequentially-incremented write address upon a first-in first-out memory device, and a read operation is performed by using a sequentially-incremented read address upon the first-in first-out memory device. The write address is cleared by a write reset signal, and the read address is cleared by a read reset signal. A delay circuit is provided to coincide an effective timing of the write reset signal in the memory cell array with that of the read reset signal in the memory cell array.

    摘要翻译： 通过在先进先出存储器件中使用顺序递增的写入地址来执行写入操作，并且通过在先进先出存储器件中使用顺序递增的读取地址来执行读取操作。 写入地址由写入复位信号清零，读取地址由读取复位信号清零。 提供延迟电路以将存储单元阵列中的写入复位信号的有效定时与存储单元阵列中的读取复位信号的有效定时重合。