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公开(公告)号：US08488367B2
公开(公告)日：2013-07-16
申请号：US13052174
申请日：2011-03-21
申请人： Takafumi Shimotori , Yoichi Minemura , Hiroshi Kanno , Takayuki Tsukamoto , Jun Nishimura , Masahiro Une
发明人： Takafumi Shimotori , Yoichi Minemura , Hiroshi Kanno , Takayuki Tsukamoto , Jun Nishimura , Masahiro Une
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C11/005 , G11C13/0064 , G11C13/0069 , G11C2213/72
摘要： According to one embodiment, a method for controlling a semiconductor device comprises determining a select bit number for a group of memory cells each includes a variable-resistance element, setting a first voltage corresponding to the select bit number, applying the set first voltage to the memory cell group, and performing verify read on the memory cell group to which the first voltage has been applied and determining whether or not the memory cell group passes the verify read. If the memory cell group is determined not to pass the verify read, the number of bits corresponding to passed memory cells is subtracted from the select bit number, and the first voltage corresponding to the decreased select bit number is set again.
摘要翻译： 根据一个实施例，一种用于控制半导体器件的方法包括确定一组存储器单元的选择位数，每个存储单元包括可变电阻元件，设置与选择位数对应的第一电压，将所设置的第一电压施加到 存储单元组，并对已经施加了第一电压的存储单元组执行验证读取，并确定存储单元组是否通过验证读取。 如果确定存储单元组不通过验证读取，则从选择位数中减去与传递的存储器单元相对应的位数，并且再次设置与减小的选择位数相对应的第一电压。
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公开(公告)号：US20110235400A1
公开(公告)日：2011-09-29
申请号：US13052174
申请日：2011-03-21
申请人： Takafumi Shimotori , Yoichi Minemura , Hiroshi Kanno , Takayuki Tsukamoto , Jun Nishimura , Masahiro Une
发明人： Takafumi Shimotori , Yoichi Minemura , Hiroshi Kanno , Takayuki Tsukamoto , Jun Nishimura , Masahiro Une
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C11/005 , G11C13/0064 , G11C13/0069 , G11C2213/72
摘要： According to one embodiment, a method for controlling a semiconductor device comprises determining a select bit number for a group of memory cells each includes a variable-resistance element, setting a first voltage corresponding to the select bit number, applying the set first voltage to the memory cell group, and performing verify read on the memory cell group to which the first voltage has been applied and determining whether or not the memory cell group passes the verify read. If the memory cell group is determined not to pass the verify read, the number of bits corresponding to passed memory cells is subtracted from the select bit number, and the first voltage corresponding to the decreased select bit number is set again.
摘要翻译： 根据一个实施例，一种用于控制半导体器件的方法包括确定一组存储器单元的选择位数，每个存储单元包括可变电阻元件，设置与选择位数对应的第一电压，将所设置的第一电压施加到 存储单元组，并对已经施加了第一电压的存储单元组执行验证读取，并确定存储单元组是否通过验证读取。 如果确定存储单元组不通过验证读取，则从选择位数中减去与传递的存储器单元相对应的位数，并且再次设置与减小的选择位数相对应的第一电压。
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公开(公告)号：US08274822B2
公开(公告)日：2012-09-25
申请号：US13018757
申请日：2011-02-01
申请人： Takayuki Tsukamoto , Yoichi Minemura , Natsuki Kikuchi , Mitsuru Sato , Hiroshi Kanno , Takafumi Shimotori
发明人： Takayuki Tsukamoto , Yoichi Minemura , Natsuki Kikuchi , Mitsuru Sato , Hiroshi Kanno , Takafumi Shimotori
IPC分类号： G11C11/00
CPC分类号： H01L45/04 , G11C5/147 , G11C13/0007 , G11C13/0038 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/72 , H01L45/145
摘要： According to one embodiment, a nonvolatile memory device includes a memory unit and a control unit. The memory unit includes first and second interconnects, and a memory cell. The second interconnect is non-parallel to the first interconnect. The memory cell includes a resistance change layer provided at an intersection between the first and second interconnects. The control unit is connected to the first and second interconnects to supply voltage and current to the resistance change layer. The control unit increases an upper limit of a current supplied to the first interconnect based on a change of a potential of the first interconnect when applying a set operation voltage to the first interconnect in a set operation of changing the resistance change layer from a first state with a first resistance value to a second state with a second resistance value being less than the first resistance value.
摘要翻译： 根据一个实施例，非易失性存储器件包括存储器单元和控制单元。 存储单元包括第一和第二互连以及存储单元。 第二互连与第一互连不平行。 存储单元包括设置在第一和第二互连之间的交叉点处的电阻变化层。 控制单元连接到第一和第二互连以向电阻变化层提供电压和电流。 控制单元在将电阻变化层从第一状态变化的设定动作中，基于第一配线的电位的变化来增大提供给第一配线的电流的上限， 具有第一电阻值到第二状态，其中第二电阻值小于第一电阻值。
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公开(公告)号：US20120224411A1
公开(公告)日：2012-09-06
申请号：US13350067
申请日：2012-01-13
IPC分类号： G11C11/21
CPC分类号： G11C13/0002 , G11C13/0028 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0083
摘要： According to one embodiment, a control unit multiple-selects a first line for every N lines from a plurality of first lines. N is an integer greater than or equal to one. The control unit sets the multiple-selected first lines to a selection potential, and fixes potentials of non-selected first lines at least adjacent to the multiple-selected first lines at a first timing. The control unit causes the multiple-selected first lines to be in a floating state at a second timing after the first timing. The control unit selects one second line from the plurality of second lines and sets the one second line to a forming potential at a third timing after the second timing.
摘要翻译： 根据一个实施例，控制单元从多条第一行为每N条线选择第一行。 N是大于或等于1的整数。 控制单元将多个选择的第一行设置为选择电位，并且在第一定时将至少与多个选择的第一行相邻的未选择的第一行的电位进行固定。 控制单元使第一定时后的第二定时使多选第一行处于浮动状态。 控制单元从多条第二行中选择一条第二行，并在第二定时之后的第三定时将一条第二行设置成一个形成电位。
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15.发明授权Non-volatile semiconductor memory device and method of controlling non-volatile semiconductor memory device 有权非挥发性半导体存储器件及非易失性半导体存储器件的控制方法公开(公告)号：US08279655B2
公开(公告)日：2012-10-02
申请号：US12885013
申请日：2010-09-17
CPC分类号： G11C8/10 , G11C13/0007 , G11C13/0069 , G11C29/50016 , G11C2013/0083 , G11C2213/31 , G11C2213/32 , G11C2213/72
摘要： According to an embodiment, there are provided a non-volatile semiconductor memory device includes: a memory cell array; a control circuit performing a series of operations to each memory cell and determining, as a defective memory cell, a memory cell whose data retention property does not satisfy a criteria, the series of operations including an operation applying a first bias to the memory cell in a forward direction, and including an operation thereafter applying a second bias to the memory cell in a reverse direction; a storage unit storing an address of the defective memory cell; and an address control unit performing a control to avoid storing data in the defective memory cell whose address is stored in the storage unit.
摘要翻译： 根据实施例，提供了一种非易失性半导体存储器件，包括：存储单元阵列; 对每个存储单元执行一系列操作的控制电路，并且确定其数据保持特性不满足标准的存储单元作为缺陷存储单元，所述一系列操作包括对存储单元施加第一偏置的操作 并且包括在相反方向上向存储单元施加第二偏置的操作; 存储单元，存储有缺陷的存储单元的地址; 以及地址控制单元，执行控制以避免将数据存储在其地址存储在存储单元中的有缺陷的存储单元中。
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公开(公告)号：US08804402B2
公开(公告)日：2014-08-12
申请号：US13722210
申请日：2012-12-20
IPC分类号： G11C13/00
CPC分类号： G11C13/0097 , G11C13/0007 , G11C13/0069 , G11C2213/71 , G11C2213/72
摘要： A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including a plurality of memory cells provided at each of intersections of a plurality of first lines and a plurality of second lines; and a control circuit applying a selected first line voltage to a selected first line, an adjacent unselected first line voltage which is larger than the selected first line voltage to an adjacent unselected first line, and an unselected first line voltage which is larger than the adjacent unselected first line voltage to an unselected first line, and applying a selected second line voltage which is larger than the selected first line voltage to a selected second line and an unselected second line voltage which is smaller than the selected second line voltage to an unselected second line.
摘要翻译： 根据实施例的非易失性半导体存储器件包括：存储单元阵列，包括设置在多个第一线和多条第二线的每个交点处的多个存储单元; 以及控制电路，将所选择的第一线电压施加到所选择的第一线，相对于相邻未选择的第一线大于所选择的第一线电压的相邻未选择的第一线电压，以及大于相邻的未选择的第一线电压的未选择的第一线电压 将未选择的第一线电压提供给未选择的第一线，以及将选择的第二线电压大于所选择的第一线电压至选定的第二线，以及将小于所选择的第二线电压的未选择的第二线电压施加到未选择的第二线电压 线。
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公开(公告)号：US08665634B2
公开(公告)日：2014-03-04
申请号：US13600448
申请日：2012-08-31
CPC分类号： G11C13/0002 , G11C11/1673 , G11C11/419 , G11C13/0004 , G11C13/0007 , G11C13/0009 , G11C13/0011 , G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/72
摘要： A memory cell array includes memory cells disposed at intersections of first lines and second lines, and each having a rectifying element and a variable resistance element connected in series. A control circuit, when performing an operation to change retained data, applies a first voltage to a selected first line and applies a second voltage to a selected second line; furthermore, applies a third voltage to a non-selected first line; and, moreover, applies a fourth voltage larger than the third voltage to a non-selected second line. An absolute value of a difference between the third voltage and the fourth voltage is set smaller than an absolute value of a difference between the first voltage and the second voltage by an amount of an offset voltage. A value of the offset voltage increases as the absolute value of the difference between the first and second voltages increases.
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公开(公告)号：US20140063906A1
公开(公告)日：2014-03-06
申请号：US13722210
申请日：2012-12-20
IPC分类号： G11C13/00
CPC分类号： G11C13/0097 , G11C13/0007 , G11C13/0069 , G11C2213/71 , G11C2213/72
摘要： A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including a plurality of memory cells provided at each of intersections of a plurality of first lines and a plurality of second lines;and a control circuit applying a selected first line voltage to a selected first line, an adjacent unselected first line voltage which is larger than the selected first line voltage to an adjacent unselected first line, and an unselected first line voltage which is larger than the adjacent unselected first line voltage to an unselected first line, and applying a selected second line voltage which is larger than the selected first line voltage to a selected second line and an unselected second line voltage which is smaller than the selected second line voltage to an unselected second line.
摘要翻译： 根据实施例的非易失性半导体存储器件包括：存储单元阵列，包括设置在多个第一线和多条第二线的每个交点处的多个存储单元; 以及控制电路，将所选择的第一线电压施加到所选择的第一线，相对于相邻未选择的第一线大于所选择的第一线电压的相邻未选择的第一线电压，以及大于相邻的未选择的第一线电压的未选择的第一线电压 将未选择的第一线电压提供给未选择的第一线，以及将选择的第二线电压大于所选择的第一线电压至选定的第二线，以及将小于所选择的第二线电压的未选择的第二线电压施加到未选择的第二线电压 线。
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公开(公告)号：US20110103128A1
公开(公告)日：2011-05-05
申请号：US12882685
申请日：2010-09-15
CPC分类号： G11C7/02 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0064 , G11C13/0097 , G11C2213/31 , G11C2213/71 , G11C2213/72
摘要： Nonvolatile semiconductor memory device of an embodiment includes: a memory cell array including a plurality of first and second lines intersecting each other and plural memory cells provided at intersections of the first and second lines and having data written and erased upon application of voltages of the same polarity; and a writing circuit configured to select first and second lines and supply a set or reset pulse to the memory cell through the selected first and second lines. In an erase operation, the writing circuit repeatedly supplies the reset pulse to a selected memory cell until data is erased, by increasing or decreasing voltage level and voltage application time of the reset pulse within a reset region. The reset region, or an aggregate of combinations of voltage level and voltage application time of the reset pulse, is a region where voltage level and voltage application time are negatively correlated.
摘要翻译： 一个实施例的非易失性半导体存储器件包括：存储单元阵列，包括彼此相交的多个第一和第二线，以及设置在第一和第二线的交点处的多个存储单元，并且在施加相同的电压时写入和擦除数据 极性; 以及写入电路，被配置为选择第一和第二行，并且通过所选择的第一和第二行向存储器单元提供置位或复位脉冲。 在擦除操作中，写入电路通过增加或减小复位区域内的复位脉冲的电压电平和电压施加时间，将复位脉冲重复地提供给所选择的存储单元，直到数据被擦除。 复位区域或复位脉冲的电压电平和电压施加时间的组合的总和是电压电平和电压施加时间呈负相关的区域。
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20.发明申请NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DATA WRITE/DATA ERASE THEREIN 有权非易失性半导体存储器件及数据写入/数据擦除方法公开(公告)号：US20110026299A1
公开(公告)日：2011-02-03
申请号：US12713667
申请日：2010-02-26
CPC分类号： G11C5/025 , G11C13/0007 , G11C13/003 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2013/0073 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76
摘要： A nonvolatile semiconductor memory device comprises: a plurality of first lines; a plurality of second lines; a plurality of memory cells each disposed at each of crossing-points of the first lines and the second lines and each comprising a variable resistor and a bi-directional diode; and a voltage control circuit configured to control a voltage of selected one of the first lines, unselected ones of the first lines, selected one of the second lines, and unselected ones of the second lines, respectively. The variable resistor is configured to change its resistance value depending on a polarity of a voltage applied thereto. The voltage control circuit is configured to apply a voltage pulse to the selected one of the first lines and to connect a capacitor of a certain capacitance to one end of the selected one of the second lines.
摘要翻译： 非易失性半导体存储器件包括：多条第一线; 多条第二线; 多个存储单元，每个存储单元分别设置在第一线和第二线的交叉点的每一个处，并且每个存储单元包括可变电阻器和双向二极管; 以及电压控制电路，被配置为分别控制所选择的第一行，未选择的第一行，所选择的第二行和未选择的第二行中的一个的电压。 可变电阻器被配置为根据施加到其的电压的极性来改变其电阻值。 电压控制电路被配置为向所选择的第一线中的一个施加电压脉冲，并且将一定电容的电容器连接到所选择的一条第二线路的一端。
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