公开(公告)号：US08605485B2

公开(公告)日：2013-12-10

申请号：US13350067

申请日：2012-01-13

申请人： Hiroshi Kanno ,  Takafumi Shimotori ,  Yoichi Minemura ,  Takahiko Sasaki ,  Takayuki Tsukamoto

发明人： Hiroshi Kanno ,  Takafumi Shimotori ,  Yoichi Minemura ,  Takahiko Sasaki ,  Takayuki Tsukamoto

IPC分类号： G11C11/00

CPC分类号： G11C13/0002 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0083

摘要： According to one embodiment, a control unit multiple-selects a first line for every N lines from a plurality of first lines. N is an integer greater than or equal to one. The control unit sets the multiple-selected first lines to a selection potential, and fixes potentials of non-selected first lines at least adjacent to the multiple-selected first lines at a first timing. The control unit causes the multiple-selected first lines to be in a floating state at a second timing after the first timing. The control unit selects one second line from the plurality of second lines and sets the one second line to a forming potential at a third timing after the second timing.

摘要翻译： 根据一个实施例，控制单元从多条第一行为每N条线选择第一行。 N是大于或等于1的整数。 控制单元将多个选择的第一行设置为选择电位，并且在第一定时将至少与多个选择的第一行相邻的未选择的第一行的电位进行固定。 控制单元使第一定时后的第二定时使多选第一行处于浮动状态。 控制单元从多条第二行中选择一条第二行，并在第二定时之后的第三定时将一条第二行设置成一个形成电位。

公开(公告)号：US08279655B2

公开(公告)日：2012-10-02

申请号：US12885013

申请日：2010-09-17

申请人： Hiroshi Kanno ,  Takayuki Tsukamoto ,  Takahiko Sasaki ,  Takafumi Shimotori

发明人： Hiroshi Kanno ,  Takayuki Tsukamoto ,  Takahiko Sasaki ,  Takafumi Shimotori

IPC分类号： G11C11/00 ,  G11C29/04

CPC分类号： G11C8/10 ,  G11C13/0007 ,  G11C13/0069 ,  G11C29/50016 ,  G11C2013/0083 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/72

摘要： According to an embodiment, there are provided a non-volatile semiconductor memory device includes: a memory cell array; a control circuit performing a series of operations to each memory cell and determining, as a defective memory cell, a memory cell whose data retention property does not satisfy a criteria, the series of operations including an operation applying a first bias to the memory cell in a forward direction, and including an operation thereafter applying a second bias to the memory cell in a reverse direction; a storage unit storing an address of the defective memory cell; and an address control unit performing a control to avoid storing data in the defective memory cell whose address is stored in the storage unit.

摘要翻译： 根据实施例，提供了一种非易失性半导体存储器件，包括：存储单元阵列; 对每个存储单元执行一系列操作的控制电路，并且确定其数据保持特性不满足标准的存储单元作为缺陷存储单元，所述一系列操作包括对存储单元施加第一偏置的操作 并且包括在相反方向上向存储单元施加第二偏置的操作; 存储单元，存储有缺陷的存储单元的地址; 以及地址控制单元，执行控制以避免将数据存储在其地址存储在存储单元中的有缺陷的存储单元中。

公开(公告)号：US20120224411A1

公开(公告)日：2012-09-06

申请号：US13350067

申请日：2012-01-13

申请人： Hiroshi KANNO ,  Takafumi Shimotori ,  Yoichi Minemura ,  Takahiko Sasaki ,  Takayuki Tsukamoto

发明人： Hiroshi KANNO ,  Takafumi Shimotori ,  Yoichi Minemura ,  Takahiko Sasaki ,  Takayuki Tsukamoto

IPC分类号： G11C11/21

CPC分类号： G11C13/0002 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0083

摘要： According to one embodiment, a control unit multiple-selects a first line for every N lines from a plurality of first lines. N is an integer greater than or equal to one. The control unit sets the multiple-selected first lines to a selection potential, and fixes potentials of non-selected first lines at least adjacent to the multiple-selected first lines at a first timing. The control unit causes the multiple-selected first lines to be in a floating state at a second timing after the first timing. The control unit selects one second line from the plurality of second lines and sets the one second line to a forming potential at a third timing after the second timing.

摘要翻译： 根据一个实施例，控制单元从多条第一行为每N条线选择第一行。 N是大于或等于1的整数。 控制单元将多个选择的第一行设置为选择电位，并且在第一定时将至少与多个选择的第一行相邻的未选择的第一行的电位进行固定。 控制单元使第一定时后的第二定时使多选第一行处于浮动状态。 控制单元从多条第二行中选择一条第二行，并在第二定时之后的第三定时将一条第二行设置成一个形成电位。

公开(公告)号：US08675388B2

公开(公告)日：2014-03-18

申请号：US13233679

申请日：2011-09-15

申请人： Yoichi Minemura ,  Takayuki Tsukamoto ,  Takafumi Shimotori ,  Hiroshi Kanno ,  Natsuki Kikuchi ,  Mitsuru Sato

发明人： Yoichi Minemura ,  Takayuki Tsukamoto ,  Takafumi Shimotori ,  Hiroshi Kanno ,  Natsuki Kikuchi ,  Mitsuru Sato

IPC分类号： G11C11/00

CPC分类号： G11C5/063 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0069 ,  G11C29/025 ,  G11C29/028 ,  G11C2013/0083 ,  G11C2213/71

摘要： A nonvolatile semiconductor memory device includes: a memory cell array including plural first lines, plural second lines, and plural memory cells each including a variable resistance element; a first decoder connected to at least one ends of the plurality of first lines and configured to select at least one of the first lines; at least one pair of second decoders connected to both ends of the plurality of second lines and configured such that one of the pair of second decoders is selected for selecting the second lines according to a distance between the one of the first lines selected by the first decoder and the both ends of the second lines; and a voltage application circuit configured to apply a certain voltage between the first line and the second line selected by the first decoder and the second decoder.

摘要翻译： 非易失性半导体存储器件包括：包括多个第一线，多个第二线和多个存储单元的存储单元阵列，每个存储单元包括可变电阻元件; 第一解码器，连接到所述多条第一线的至少一端，并被配置为选择所述第一线中的至少一条线; 至少一对第二解码器，连接到所述多个第二线路的两端，并且被配置为使得所述一对第二解码器中的一个被选择用于根据所述第一线选择的所述第一线之间的距离来选择所述第二线 解码器和第二行的两端; 以及电压施加电路，被配置为在由第一解码器和第二解码器选择的第一线和第二线之间施加一定电压。

公开(公告)号：US09099180B2

公开(公告)日：2015-08-04

申请号：US13599301

申请日：2012-08-30

申请人： Yoichi Minemura ,  Takayuki Tsukamoto ,  Takafumi Shimotori ,  Hiroshi Kanno ,  Tomonori Kurosawa ,  Mizuki Kaneko

发明人： Yoichi Minemura ,  Takayuki Tsukamoto ,  Takafumi Shimotori ,  Hiroshi Kanno ,  Tomonori Kurosawa ,  Mizuki Kaneko

IPC分类号： G11C11/00 ,  G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0097 ,  G11C2213/71 ,  G11C2213/72

摘要： According to one embodiment, a semiconductor memory device includes a plurality of cell array blocks and a control circuit. The control circuit sets a selected bit line to have 0 volt, applies a first electric potential which is higher than 0 volt to a selected word line, applies a second electric potential which is higher than 0 volt and lower than the first electric potential to non-selected word lines other than the selected word line, applies a third electric potential which is 0 volt or more and lower than the second electric potential to a non-selected bit line adjacent to the selected bit line in an adjacent cell array block, applies the second electric potential to non-selected bit lines other than the non-selected bit line to which the third electric potential is applied, and changes a resistance status of the resistance variable film of the selected memory cell.

摘要翻译： 根据一个实施例，半导体存储器件包括多个单元阵列块和控制电路。 控制电路将所选择的位线设置为具有0伏特，对所选择的字线施加高于0伏的第一电位，将比第一电位高于0伏且低于第一电位的第二电位施加到非 - 除了所选字线以外的选定字线，将相邻单元阵列块中与选定位线相邻的未选位线施加0伏以上且低于第2电位的第3电位， 对除了施加了第三电位的未选位线之外的非选择位线的第二电位，并且改变所选存储单元的电阻变化膜的电阻状态。

公开(公告)号：US08837199B2

公开(公告)日：2014-09-16

申请号：US13599265

申请日：2012-08-30

申请人： Hiroshi Kanno ,  Yoichi Minemura ,  Mizuki Kaneko ,  Tomonori Kurosawa ,  Takafumi Shimotori ,  Takayuki Tsukamoto

发明人： Hiroshi Kanno ,  Yoichi Minemura ,  Mizuki Kaneko ,  Tomonori Kurosawa ,  Takafumi Shimotori ,  Takayuki Tsukamoto

IPC分类号： G11C11/00 ,  G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0097 ,  G11C2213/71 ,  G11C2213/72

摘要： According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a plurality of memory cells, a plurality of wires, and a control circuit. The control circuit allows a first current to change a state to flow on a selected cell by applying a first potential difference between a pair of wires that sandwich the selected cell selected from the plurality of memory cells with respect to the semiconductor substrate vertically, and allows a second current lower than the first current to flow on an non-selected cell in the same direction as the direction of the first current by applying a second potential difference between a pair of wires that sandwich the non-selected cell connected to a wire shared with the selected cell on a different layer from the selected cell.

摘要翻译： 根据一个实施例，半导体存储器件包括半导体衬底，多个存储单元，多根导线和控制电路。 控制电路允许第一电流通过在相对于半导体衬底垂直地夹持从多个存储单元中选择的所选择的单元的一对导线之间施加第一电位差来改变选定单元上的状态，并允许 低于第一电流的第二电流，在与所述第一电流的方向相同的方向上在未选择的单元上流动，通过在连接到共享的线的未选择的单元之间施加一对导线之间的第二电位差 所选单元格与选定单元格不同的图层。

公开(公告)号：US08488367B2

公开(公告)日：2013-07-16

申请号：US13052174

申请日：2011-03-21

申请人： Takafumi Shimotori ,  Yoichi Minemura ,  Hiroshi Kanno ,  Takayuki Tsukamoto ,  Jun Nishimura ,  Masahiro Une

发明人： Takafumi Shimotori ,  Yoichi Minemura ,  Hiroshi Kanno ,  Takayuki Tsukamoto ,  Jun Nishimura ,  Masahiro Une

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C11/005 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2213/72

摘要： According to one embodiment, a method for controlling a semiconductor device comprises determining a select bit number for a group of memory cells each includes a variable-resistance element, setting a first voltage corresponding to the select bit number, applying the set first voltage to the memory cell group, and performing verify read on the memory cell group to which the first voltage has been applied and determining whether or not the memory cell group passes the verify read. If the memory cell group is determined not to pass the verify read, the number of bits corresponding to passed memory cells is subtracted from the select bit number, and the first voltage corresponding to the decreased select bit number is set again.

摘要翻译： 根据一个实施例，一种用于控制半导体器件的方法包括确定一组存储器单元的选择位数，每个存储单元包括可变电阻元件，设置与选择位数对应的第一电压，将所设置的第一电压施加到 存储单元组，并对已经施加了第一电压的存储单元组执行验证读取，并确定存储单元组是否通过验证读取。 如果确定存储单元组不通过验证读取，则从选择位数中减去与传递的存储器单元相对应的位数，并且再次设置与减小的选择位数相对应的第一电压。

公开(公告)号：US20110235400A1

公开(公告)日：2011-09-29

申请号：US13052174

申请日：2011-03-21

申请人： Takafumi Shimotori ,  Yoichi Minemura ,  Hiroshi Kanno ,  Takayuki Tsukamoto ,  Jun Nishimura ,  Masahiro Une

发明人： Takafumi Shimotori ,  Yoichi Minemura ,  Hiroshi Kanno ,  Takayuki Tsukamoto ,  Jun Nishimura ,  Masahiro Une

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C11/005 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2213/72

摘要： According to one embodiment, a method for controlling a semiconductor device comprises determining a select bit number for a group of memory cells each includes a variable-resistance element, setting a first voltage corresponding to the select bit number, applying the set first voltage to the memory cell group, and performing verify read on the memory cell group to which the first voltage has been applied and determining whether or not the memory cell group passes the verify read. If the memory cell group is determined not to pass the verify read, the number of bits corresponding to passed memory cells is subtracted from the select bit number, and the first voltage corresponding to the decreased select bit number is set again.

摘要翻译： 根据一个实施例，一种用于控制半导体器件的方法包括确定一组存储器单元的选择位数，每个存储单元包括可变电阻元件，设置与选择位数对应的第一电压，将所设置的第一电压施加到 存储单元组，并对已经施加了第一电压的存储单元组执行验证读取，并确定存储单元组是否通过验证读取。 如果确定存储单元组不通过验证读取，则从选择位数中减去与传递的存储器单元相对应的位数，并且再次设置与减小的选择位数相对应的第一电压。

公开(公告)号：US09076525B2

公开(公告)日：2015-07-07

申请号：US13597773

申请日：2012-08-29

申请人： Mizuki Kaneko ,  Tomonori Kurosawa ,  Yoichi Minemura ,  Hiroshi Kanno ,  Takafumi Shimotori ,  Takayuki Tsukamoto

发明人： Mizuki Kaneko ,  Tomonori Kurosawa ,  Yoichi Minemura ,  Hiroshi Kanno ,  Takafumi Shimotori ,  Takayuki Tsukamoto

IPC分类号： G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C2213/72

摘要： A semiconductor storage device includes a memory cell array, and a control circuit. The memory cell array has memory cells including variable resistive elements disposed at intersections of a plurality of first lines and a plurality of second lines. The control circuit performs a set pulse applying operation, and a cure pulse applying operation. The set pulse applying operation applies a set pulse to a variable resistive element so as to cause the variable resistive element to transition from a high resistance state to a low resistance state. The cure pulse applying operation applies a cure pulse to the variable resistive element. The cure pulse has a polarity that is opposite of a polarity of the set pulse, and is larger than the set pulse.

摘要翻译： 半导体存储装置包括存储单元阵列和控制电路。 存储单元阵列具有包括设置在多个第一线和多条第二线的交叉处的可变电阻元件的存储单元。 控制电路执行设定脉冲施加操作和固化脉冲施加操作。 设置脉冲施加操作将设定脉冲施加到可变电阻元件，以使可变电阻元件从高电阻状态转变到低电阻状态。 固化脉冲施加操作对可变电阻元件施加固化脉冲。 固化脉冲具有与设定脉冲的极性相反的极性，并且大于设定脉冲。

公开(公告)号：US08861265B2

公开(公告)日：2014-10-14

申请号：US13597814

申请日：2012-08-29

申请人： Tomonori Kurosawa ,  Mizuki Kaneko ,  Takafumi Shimotori ,  Takayuki Tsukamoto ,  Yoichi Minemura ,  Hiroshi Kanno

发明人： Tomonori Kurosawa ,  Mizuki Kaneko ,  Takafumi Shimotori ,  Takayuki Tsukamoto ,  Yoichi Minemura ,  Hiroshi Kanno

IPC分类号： G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2013/0083 ,  G11C2213/72

摘要： In a memory cell array, memory cells each including a variable resistance element are arranged at crossing portions between a plurality of first wiring and a plurality of second wirings. A control circuit executes a set operation, a reset operation, and a training operation. In the set operation, a set pulse is applied to the variable resistance element to change the variable resistance element from a high resistance state to a low resistance state. In the reset operation, a reset pulse having an opposite polarity to the polarity of the set pulse is applied to the variable resistance element to change the variable resistance element from the low resistance state to the high resistance state. In the training operation, the set pulse and the reset pulse are continuously applied to the variable resistance element.

摘要翻译： 在存储单元阵列中，包括可变电阻元件的存储单元布置在多个第一布线和多个第二布线之间的交叉部分处。 控制电路执行设定操作，复位操作和训练操作。 在设定动作中，向可变电阻元件施加设定脉冲，将可变电阻元件从高电阻状态变为低电阻状态。 在复位操作中，将具有与设定脉冲的极性相反的极性的复位脉冲施加到可变电阻元件，以将可变电阻元件从低电阻状态改变为高电阻状态。 在训练操作中，将设定脉冲和复位脉冲连续施加到可变电阻元件。