公开(公告)号：US20100207194A1

公开(公告)日：2010-08-19

申请号：US12706127

申请日：2010-02-16

申请人： Hiroyasu TANAKA ,  Hideaki AOCHI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Masaru KITO ,  Yoshiaki FUKUZUMI ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Tomoko FUJIWARA ,  Junya MATSUNAMI ,  Ryouhei KIRISAWA

发明人： Hiroyasu TANAKA ,  Hideaki AOCHI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Masaru KITO ,  Yoshiaki FUKUZUMI ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Tomoko FUJIWARA ,  Junya MATSUNAMI ,  Ryouhei KIRISAWA

IPC分类号： H01L27/115 ,  H01L21/8246

CPC分类号： H01L29/792 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833

摘要： A nonvolatile semiconductor memory device includes: a semiconductor substrate; a stacked body provided on the semiconductor substrate, the stacked body having electrode films and insulating films being alternately stacked; a first and second semiconductor pillars; and a first and second charge storage layers. The first and second semiconductor pillars are provided inside a through hole penetrating through the stacked body in a stacking direction of the stacked body. The through hole has a cross section of an oblate circle, when cutting in a direction perpendicular to the stacking direction. The first and second semiconductor pillars face each other in a major axis direction of the first oblate circle. The first and second semiconductor pillars extend in the stacking direction. The first and second charge storage layers are provided between the electrode film and the first and second semiconductor pillars, respectively.

摘要翻译： 非易失性半导体存储器件包括：半导体衬底; 设置在所述半导体基板上的层叠体，具有交替堆叠的电极膜和绝缘膜的层叠体， 第一和第二半导体柱; 以及第一和第二电荷存储层。 第一半导体柱和第二半导体柱设置在层叠体的层叠方向上贯穿层叠体的贯通孔内。 当沿垂直于堆叠方向的方向切割时，通孔具有扁圆形的横截面。 第一和第二半导体柱在第一扁圆的长轴方向上彼此面对。 第一和第二半导体柱沿层叠方向延伸。 第一和第二电荷存储层分别设置在电极膜和第一和第二半导体柱之间。

公开(公告)号：US20100038703A1

公开(公告)日：2010-02-18

申请号：US12501142

申请日：2009-07-10

申请人： Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KITO ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hideaki AOCHI

发明人： Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KITO ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hideaki AOCHI

IPC分类号： H01L29/792 ,  H01L27/112

CPC分类号： H01L29/792 ,  G11C5/02 ,  G11C5/025 ,  G11C5/063 ,  G11C8/14 ,  G11C16/0483 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/42348 ,  H01L29/7926

摘要： A memory string has a semiconductor layer with a joining portion that is formed to join a plurality of columnar portions extending in a vertical direction with respect to a substrate and lower ends of the plurality of columnar portions. First conductive layers are formed in a laminated fashion to surround side surfaces of the columnar portions and an electric charge storage layer, and function as control electrodes of memory cells. A second conductive layer is formed around the plurality of columnar portions via a gate insulation film, and functions as control electrodes of selection transistors. Bit lines are formed to be connected to the plurality of columnar portions, respectively, with a second direction orthogonal to a first direction taken as a longitudinal direction.

摘要翻译： 存储器串具有半导体层，其具有接合部分，该接合部分形成为连接相对于衬底在垂直方向上延伸的多个柱状部分和多个柱状部分的下端。 第一导电层以叠层的方式形成以包围柱状部分的侧表面和电荷存储层，并且用作存储单元的控制电极。 通过栅极绝缘膜在多个柱状部分周围形成第二导电层，并且用作选择晶体管的控制电极。 位线分别形成为与第一方向正交的第二方向作为纵向连接到多个柱状部分。

公开(公告)号：US20110227140A1

公开(公告)日：2011-09-22

申请号：US12834390

申请日：2010-07-12

申请人： Megumi ISHIDUKI ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hideaki Aochi

发明人： Megumi ISHIDUKI ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hideaki Aochi

IPC分类号： H01L27/115 ,  H01L21/8246

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a memory film, and a SiGe film. The stacked body includes a plurality of conductive layers and a plurality of insulating layers alternately stacked above the substrate. The memory film includes a charge storage film. The memory film is provided on a sidewall of a memory hole punched through the stacked body. The SiGe film is provided inside the memory film in the memory hole.

摘要翻译： 根据一个实施例，半导体存储器件包括衬底，层叠体，存储膜和SiGe膜。 层叠体包括交替层叠在基板的上方的多个导电层和多个绝缘层。 记忆膜包括电荷存储膜。 记忆膜设置在穿过堆叠体的冲击的存储孔的侧壁上。 SiGe膜被提供在存储器孔内的记忆膜内部。

公开(公告)号：US20130075805A1

公开(公告)日：2013-03-28

申请号：US13419984

申请日：2012-03-14

申请人： Mitsuru SATO ,  Megumi ISHIDUKI ,  Masaru KIDOH ,  Atsushi KONNO ,  Yoshihiro AKUTSU ,  Masaru KITO ,  Yoshiaki FUKUZUMI ,  Ryota KATSUMATA

发明人： Mitsuru SATO ,  Megumi ISHIDUKI ,  Masaru KIDOH ,  Atsushi KONNO ,  Yoshihiro AKUTSU ,  Masaru KITO ,  Yoshiaki FUKUZUMI ,  Ryota KATSUMATA

IPC分类号： H01L29/792 ,  H01L21/425

CPC分类号： H01L29/7926 ,  H01L21/265 ,  H01L27/11582 ,  H01L29/0676 ,  H01L29/66833

摘要： According to one embodiment, a method for manufacturing a nonvolatile semiconductor storage device includes; forming a first and a second stacked bodies; forming a through hole penetrating through the first stacked body, a second portion communicating with the first portion and penetrating through a select gate, and a third portion communicating with the second portion and penetrating through a second insulating layer; forming a memory film, a gate insulating film, and a channel body; forming a third insulating layer inside the channel body; forming a first embedded portion above a boundary portion inside the third portion; exposing the channel body by removing part of the first embedded portion and part of the third insulating layer in the third portion; and embedding a second embedded portion including silicon having higher impurity concentration than the first embedded portion above the first embedded portion inside the third portion.

摘要翻译： 根据一个实施例，一种用于制造非易失性半导体存储装置的方法包括： 形成第一和第二堆叠体; 形成穿过所述第一层叠体的通孔，与所述第一部分连通并穿过选择栅极的第二部分，以及与所述第二部分连通并穿透第二绝缘层的第三部分; 形成记忆膜，栅极绝缘膜和通道体; 在通道体内形成第三绝缘层; 在第三部分内部的边界部分上方形成第一嵌入部分; 通过去除第三部分中的第一嵌入部分和第三绝缘层的一部分的一部分来暴露通道体; 以及在所述第三部分内部嵌入包含比所述第一嵌入部分上方的所述第一嵌入部分杂质浓度高的硅的第二嵌入部分。

公开(公告)号：US20130056815A1

公开(公告)日：2013-03-07

申请号：US13420745

申请日：2012-03-15

申请人： Megumi ISHIDUKI ,  Masaru Kidoh ,  Mitsuru Sato ,  Masaru Kito ,  Ryota Katsumata

发明人： Megumi ISHIDUKI ,  Masaru Kidoh ,  Mitsuru Sato ,  Masaru Kito ,  Ryota Katsumata

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7926 ,  H01L21/28282 ,  H01L27/11582 ,  H01L29/42344

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes: a first stacked body; a memory film; a first channel body layer provided inside the memory film; an interlayer insulating flm provided on the first stacked body; a second stacked body having a select gate electrode layer, and a second insulating layer; a gate insulating film provided on a side wall of a second hole communicating with the first hole and penetrating the second stacked body and the interlayer insulating flm in a stacking direction of the second stacked body; and a second channel body layer provided inside the gate insulating film in the second hole. A first pore diameter of the second hole at an upper end of the select gate electrode layer is smaller than a second pore diameter of the second hole at an lower end of the select gate electrode layer.

摘要翻译： 根据一个实施例，一种非易失性半导体存储器件包括：第一层叠体; 记忆膜; 设置在记忆膜内部的第一通道体层; 设置在第一层叠体上的层间绝缘膜; 具有选择栅电极层的第二层叠体和第二绝缘层; 栅极绝缘膜，设置在与所述第一孔连通的第二孔的侧壁上，并且在所述第二层叠体的层叠方向上贯通所述第二层叠体和所述层间绝缘膜; 以及设置在第二孔中的栅极绝缘膜内部的第二沟道体层。 选择栅电极层的上端的第二孔的第一孔径比选择栅电极层的下端的第二孔的第二孔径小。

公开(公告)号：US20120235221A1

公开(公告)日：2012-09-20

申请号：US13236723

申请日：2011-09-20

申请人： Megumi ISHIDUKI ,  Ryota Katsumata ,  Tomo Ohsawa ,  Mitsuru Sato ,  Masaru Kidoh ,  Hiroyasu Tanaka

发明人： Megumi ISHIDUKI ,  Ryota Katsumata ,  Tomo Ohsawa ,  Mitsuru Sato ,  Masaru Kidoh ,  Hiroyasu Tanaka

IPC分类号： H01L29/792 ,  H01L21/425

CPC分类号： H01L21/425 ,  H01L27/11582 ,  H01L29/7926

摘要： According to one embodiment, a semiconductor device includes a substrate, a first stacked body, a memory film, a first channel body, a second stacked body, a gate insulating film and a second channel body. A step part is formed between a side face of the select gate and the second insulating layer. A film thickness of a portion covering the step part of the second channel body is thicker than a film thickness of a portion provided between the second insulating layers of the second channel body.

摘要翻译： 根据一个实施例，半导体器件包括衬底，第一层叠体，存储膜，第一通道体，第二堆叠体，栅极绝缘膜和第二通道体。 在选择栅极的侧面和第二绝缘层之间形成台阶部。 覆盖第二通道体的台阶部分的部分的膜厚比设置在第二通道体的第二绝缘层之间的部分的膜厚度厚。